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path: root/passes/proc/proc_arst.cc
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-21
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Added "proc_arst -global_arst" featureClifford Wolf2013-11-20
* Added handling of multiple async paths in proc_arstClifford Wolf2013-10-19
* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-25
* Added help messages to proc_* passesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05