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proc
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proc_dff.cc
Commit message (
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Author
Age
*
namespace Yosys
Clifford Wolf
2014-09-27
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Using new obj iterator API in a few places
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Replaced more old SigChunk programming patterns
Clifford Wolf
2014-07-24
*
Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
Replaced depricated NEW_WIRE macro with module->addWire() calls
Clifford Wolf
2014-07-21
*
Do not create $dffsr cells with no-op resets in proc_dff
Clifford Wolf
2014-06-19
*
Added support for complex set-reset flip-flops in proc_dff
Clifford Wolf
2013-10-24
*
Improved handling of dff with async resets
Clifford Wolf
2013-10-21
*
Added dffsr support to proc_dff pass
Clifford Wolf
2013-10-18
*
fixed typos
Johann Glaser
2013-03-18
*
Added help messages to proc_* passes
Clifford Wolf
2013-03-01
*
initial import
Clifford Wolf
2013-01-05