| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 |
| * | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 |
| * | Removed RTLIL::SigSpec::optimize() | Clifford Wolf | 2014-07-23 |
| * | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 |
| * | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 |
| * | Major improvements in mem2reg and added "init" sync rules | Clifford Wolf | 2013-11-21 |
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