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proc_mux.cc
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Author
Age
*
New upstream version 0.7+20180830git0b7a184
Ruben Undheim
2018-08-30
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Squashed commit of the following:
Ruben Undheim
2016-09-23
*
Improved proc_mux performance for huge always blocks
Clifford Wolf
2015-12-02
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Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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namespace Yosys
Clifford Wolf
2014-09-27
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Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
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Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
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Using new obj iterator API in a few places
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
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Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
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Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
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Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
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Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
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Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Clifford Wolf
2014-07-23
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Clifford Wolf
2014-07-23
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Fixed memory corruption with new SigSpec API in proc_mux
Clifford Wolf
2014-07-22
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SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
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SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
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Tiny cleanup in proc_mux.cc
Clifford Wolf
2014-01-03
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Fixed handling of boolean attributes (passes)
Clifford Wolf
2013-10-24
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Added help messages to proc_* passes
Clifford Wolf
2013-03-01
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initial import
Clifford Wolf
2013-01-05