Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 | Clifford Wolf | 2014-07-23 |
* | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 | Clifford Wolf | 2014-07-23 |
* | Fixed memory corruption with new SigSpec API in proc_mux | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: using the accessor functions everywhere | Clifford Wolf | 2014-07-22 |
* | SigSpec refactoring: renamed chunks and width to __chunks and __width | Clifford Wolf | 2014-07-22 |
* | Tiny cleanup in proc_mux.cc | Clifford Wolf | 2014-01-03 |
* | Fixed handling of boolean attributes (passes) | Clifford Wolf | 2013-10-24 |
* | Added help messages to proc_* passes | Clifford Wolf | 2013-03-01 |
* | initial import | Clifford Wolf | 2013-01-05 |