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* Fixed handling of constant-true branches in proc_cleanClifford Wolf2014-08-12
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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* Using new obj iterator API in a few placesClifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
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* Manual fixes for new cell connections APIClifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
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* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
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* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
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* Fixed memory corruption with new SigSpec API in proc_muxClifford Wolf2014-07-22
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-22
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
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* Do not create $dffsr cells with no-op resets in proc_dffClifford Wolf2014-06-19
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* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-21
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* Tiny cleanup in proc_mux.ccClifford Wolf2014-01-03
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* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
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* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
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* Added "proc_arst -global_arst" featureClifford Wolf2013-11-20
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* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-24
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* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
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* Improved handling of dff with async resetsClifford Wolf2013-10-21
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* Added handling of multiple async paths in proc_arstClifford Wolf2013-10-19
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* Added dffsr support to proc_dff passClifford Wolf2013-10-18
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* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-25
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* fixed typosJohann Glaser2013-03-18
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* Added help messages to proc_* passesClifford Wolf2013-03-01
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* initial importClifford Wolf2013-01-05