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Age
*
Fixed memory corruption with new SigSpec API in proc_mux
Clifford Wolf
2014-07-22
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
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SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
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SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
Replaced depricated NEW_WIRE macro with module->addWire() calls
Clifford Wolf
2014-07-21
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Do not create $dffsr cells with no-op resets in proc_dff
Clifford Wolf
2014-06-19
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Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst
Clifford Wolf
2014-02-21
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Tiny cleanup in proc_mux.cc
Clifford Wolf
2014-01-03
*
Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
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Major improvements in mem2reg and added "init" sync rules
Clifford Wolf
2013-11-21
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Added "proc_arst -global_arst" feature
Clifford Wolf
2013-11-20
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Added support for complex set-reset flip-flops in proc_dff
Clifford Wolf
2013-10-24
*
Fixed handling of boolean attributes (passes)
Clifford Wolf
2013-10-24
*
Improved handling of dff with async resets
Clifford Wolf
2013-10-21
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Added handling of multiple async paths in proc_arst
Clifford Wolf
2013-10-19
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Added dffsr support to proc_dff pass
Clifford Wolf
2013-10-18
*
Added nosync attribute and some async reset related fixes
Clifford Wolf
2013-03-25
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fixed typos
Johann Glaser
2013-03-18
*
Added help messages to proc_* passes
Clifford Wolf
2013-03-01
*
initial import
Clifford Wolf
2013-01-05