summaryrefslogtreecommitdiff
path: root/passes/proc
Commit message (Expand)AuthorAge
* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-24
* Added log_warning() APIClifford Wolf2014-11-09
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* namespace YosysClifford Wolf2014-09-27
* Fixed handling of constant-true branches in proc_cleanClifford Wolf2014-08-12
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Using new obj iterator API in a few placesClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* Fixed memory corruption with new SigSpec API in proc_muxClifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
* Do not create $dffsr cells with no-op resets in proc_dffClifford Wolf2014-06-19
* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-21
* Tiny cleanup in proc_mux.ccClifford Wolf2014-01-03
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Added "proc_arst -global_arst" featureClifford Wolf2013-11-20
* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-24
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
* Improved handling of dff with async resetsClifford Wolf2013-10-21
* Added handling of multiple async paths in proc_arstClifford Wolf2013-10-19
* Added dffsr support to proc_dff passClifford Wolf2013-10-18
* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-25
* fixed typosJohann Glaser2013-03-18
* Added help messages to proc_* passesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05