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Commit message (Collapse)AuthorAge
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
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* Do not create $dffsr cells with no-op resets in proc_dffClifford Wolf2014-06-19
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* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-21
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* Tiny cleanup in proc_mux.ccClifford Wolf2014-01-03
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* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
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* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
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* Added "proc_arst -global_arst" featureClifford Wolf2013-11-20
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* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-24
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* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
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* Improved handling of dff with async resetsClifford Wolf2013-10-21
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* Added handling of multiple async paths in proc_arstClifford Wolf2013-10-19
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* Added dffsr support to proc_dff passClifford Wolf2013-10-18
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* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-25
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* fixed typosJohann Glaser2013-03-18
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* Added help messages to proc_* passesClifford Wolf2013-03-01
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* initial importClifford Wolf2013-01-05