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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* Fixed memory corruption with new SigSpec API in proc_muxClifford Wolf2014-07-22
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
* Do not create $dffsr cells with no-op resets in proc_dffClifford Wolf2014-06-19
* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-21
* Tiny cleanup in proc_mux.ccClifford Wolf2014-01-03
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Major improvements in mem2reg and added "init" sync rulesClifford Wolf2013-11-21
* Added "proc_arst -global_arst" featureClifford Wolf2013-11-20
* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-24
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
* Improved handling of dff with async resetsClifford Wolf2013-10-21
* Added handling of multiple async paths in proc_arstClifford Wolf2013-10-19
* Added dffsr support to proc_dff passClifford Wolf2013-10-18
* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-25
* fixed typosJohann Glaser2013-03-18
* Added help messages to proc_* passesClifford Wolf2013-03-01
* initial importClifford Wolf2013-01-05