yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	added log_header to miter and expose pass, show cell type for exposed ports	Johann Glaser	2014-05-28
*	Various improvements in expose command (added -sep and -cut)	Clifford Wolf	2014-02-09
*	Fixed handling of async reset in expose -evert-dff	Clifford Wolf	2014-02-08
*	Implemented expose -evert-dff	Clifford Wolf	2014-02-08
*	Added expose -dff	Clifford Wolf	2014-02-06
*	Added expose command	Clifford Wolf	2014-02-05