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path: root/passes/sat/sat.cc
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* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-25
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* Added sat -show-regs, -show-public, -show-allClifford Wolf2015-08-18
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* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-14
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* Spell check (by Larry Doolittle)Clifford Wolf2015-08-14
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* Fixed trailing whitespacesClifford Wolf2015-07-02
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* don't consider blackbox modules in "sat" commandClifford Wolf2015-04-18
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* Added non-std verilog assume() statementClifford Wolf2015-02-26
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* Fixed "sat -initsteps" off-by-one bugClifford Wolf2015-02-22
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* Added "sat -stepsize" and "sat -tempinduct-step"Clifford Wolf2015-02-21
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* sat docu changeClifford Wolf2015-02-21
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* When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing.Clifford Wolf2015-02-21
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* Added "sat -tempinduct-baseonly -tempinduct-inductonly"Clifford Wolf2015-02-21
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* Fixed basecase init for "sat -tempinduct"Clifford Wolf2015-02-21
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* Replaced ezDefaultSAT with ezSatPtrClifford Wolf2015-02-21
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* format fixes in "sat -dump_json"Clifford Wolf2015-02-19
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* Added "sat -dump_json" (WaveJSON format)Clifford Wolf2015-02-19
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* Improved an error messageClifford Wolf2015-01-28
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* Added "sat -show-ports"Clifford Wolf2015-01-27
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* Added log_warning() APIClifford Wolf2014-11-09
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* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
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* namespace YosysClifford Wolf2014-09-27
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* Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
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* azonenberg: Make dump_vcd save model when temporal induction fails due to ↵Clifford Wolf2014-08-24
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* Added "sat -prove-skip"Clifford Wolf2014-08-08
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
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* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
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* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-05
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* Small improvement in SAT log messagesClifford Wolf2014-03-13
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* Added "sat -dump_cnf"Clifford Wolf2014-02-18
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* Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-18
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* Added "sat -initsteps"Clifford Wolf2014-02-18
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* Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanupsClifford Wolf2014-02-17
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* Added "-dump_fail_to_vcd" argument to SAT solverAndrew Zonenberg2014-02-17
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* Added generic RTLIL::SigSpec::parse_sel() with support for selection variablesClifford Wolf2014-02-06
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* Added support for sat -show @<sel_name>Clifford Wolf2014-02-06
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* Added sat -set-init-def and sat -tempinduct-defClifford Wolf2014-02-06
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* Added sat -set-init-zero supportClifford Wolf2014-02-06
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* Added sat -verify and -falsify support for non-prove casesClifford Wolf2014-02-06
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* added sat -falsifyClifford Wolf2014-02-04
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* Fixed bug in sequential sat proofs and improved handling of assertsClifford Wolf2014-02-04
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* Addred sat option -ignore_unknown_cellsClifford Wolf2014-02-03
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