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Commit message (
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Author
Age
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
Clifford Wolf
2014-07-23
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
Removed deprecated module->new_wire()
Clifford Wolf
2014-07-21
*
Wider range of cell types supported in "share" pass
Clifford Wolf
2014-07-21
*
Use ezSAT::non_incremental() in "share" pass
Clifford Wolf
2014-07-21
*
Added support for resource sharing in mux control logic
Clifford Wolf
2014-07-20
*
Supercell creation for $div/$mod worked all along, fixed test benches
Clifford Wolf
2014-07-20
*
Fixed creation of shift supercells in "share" pass
Clifford Wolf
2014-07-20
*
Added "share" supercell creation
Clifford Wolf
2014-07-20
*
Added removing of always inactive cells to "share" pass
Clifford Wolf
2014-07-20
*
Progress in "share" pass
Clifford Wolf
2014-07-20
*
Progress in "share" pass
Clifford Wolf
2014-07-20
*
Started to implement real resource sharing
Clifford Wolf
2014-07-19