path: root/passes/sat/
Commit message (Expand)AuthorAge
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-23
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
* Wider range of cell types supported in "share" passClifford Wolf2014-07-21
* Use ezSAT::non_incremental() in "share" passClifford Wolf2014-07-21
* Added support for resource sharing in mux control logicClifford Wolf2014-07-20
* Supercell creation for $div/$mod worked all along, fixed test benchesClifford Wolf2014-07-20
* Fixed creation of shift supercells in "share" passClifford Wolf2014-07-20
* Added "share" supercell creationClifford Wolf2014-07-20
* Added removing of always inactive cells to "share" passClifford Wolf2014-07-20
* Progress in "share" passClifford Wolf2014-07-20
* Progress in "share" passClifford Wolf2014-07-20
* Started to implement real resource sharingClifford Wolf2014-07-19