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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
* Wider range of cell types supported in "share" passClifford Wolf2014-07-21
* Use ezSAT::non_incremental() in "share" passClifford Wolf2014-07-21
* Added support for resource sharing in mux control logicClifford Wolf2014-07-20
* Supercell creation for $div/$mod worked all along, fixed test benchesClifford Wolf2014-07-20
* Fixed creation of shift supercells in "share" passClifford Wolf2014-07-20
* Added "miter -equiv -flatten"Clifford Wolf2014-07-20
* Added "share" supercell creationClifford Wolf2014-07-20
* Added removing of always inactive cells to "share" passClifford Wolf2014-07-20
* Progress in "share" passClifford Wolf2014-07-20
* Progress in "share" passClifford Wolf2014-07-20
* Started to implement real resource sharingClifford Wolf2014-07-19
* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-05
* added log_header to miter and expose pass, show cell type for exposed portsJohann Glaser2014-05-28
* Small improvement in SAT log messagesClifford Wolf2014-03-13
* Fixed bug in freduce commandClifford Wolf2014-03-07
* Some minor code cleanups in freduce commandClifford Wolf2014-03-07
* Added freduce -dumpClifford Wolf2014-03-06
* Added freduce -stopClifford Wolf2014-03-06
* fixed freduce for Minisat::SimpSolver: use frozen_literal()Clifford Wolf2014-03-03
* Added "sat -dump_cnf"Clifford Wolf2014-02-18
* Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-18
* Added "sat -initsteps"Clifford Wolf2014-02-18
* Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanupsClifford Wolf2014-02-17
* Added "-dump_fail_to_vcd" argument to SAT solverAndrew Zonenberg2014-02-17
* Various improvements in expose command (added -sep and -cut)Clifford Wolf2014-02-09
* Fixed handling of async reset in expose -evert-dffClifford Wolf2014-02-08
* Implemented expose -evert-dffClifford Wolf2014-02-08
* Added generic RTLIL::SigSpec::parse_sel() with support for selection variablesClifford Wolf2014-02-06
* Added support for sat -show @<sel_name>Clifford Wolf2014-02-06
* Added sat -set-init-def and sat -tempinduct-defClifford Wolf2014-02-06