yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Fixed iopadmap help message	Clifford Wolf	2015-08-31
\|
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
\|
*	Bugfix in iopadmap	Clifford Wolf	2015-02-25
\|
*	Various small improvements to synth_xilinx	Clifford Wolf	2015-01-06
\|
*	namespace Yosys	Clifford Wolf	2014-09-27
\|
*	Bugfix in iopadmap	Clifford Wolf	2014-08-15
\|
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
\|
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
\|
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
\|
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
\|
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
\|
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at\("([^"])"\)/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
\|
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
\|
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23
\|
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23
\|
*	Added support for "blackbox" attribute to iopadmap	Clifford Wolf	2014-07-17
\|
*	Added iopadmap -bits	Clifford Wolf	2014-02-15
\|
*	Added support for i/o buffers to iopadmap	Clifford Wolf	2013-10-26
\|
*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24
\|
*	Added iopadmap pass	Clifford Wolf	2013-10-16