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* Squashed commit of the following:Ruben Undheim2016-09-23
* Fixed iopadmap help messageClifford Wolf2015-08-31
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Bugfix in iopadmapClifford Wolf2015-02-25
* Various small improvements to synth_xilinxClifford Wolf2015-01-06
* namespace YosysClifford Wolf2014-09-27
* Bugfix in iopadmapClifford Wolf2014-08-15
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* Added support for "blackbox" attribute to iopadmapClifford Wolf2014-07-17
* Added iopadmap -bitsClifford Wolf2014-02-15
* Added support for i/o buffers to iopadmapClifford Wolf2013-10-26
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
* Added iopadmap passClifford Wolf2013-10-16