yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07
*	Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)	Clifford Wolf	2013-12-29
*	Added new cell types to manual	Clifford Wolf	2013-12-28
*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28
*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24
*	Added simplemap pass	Clifford Wolf	2013-11-24