yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
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*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31
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*	Added "techmap -assert"	Clifford Wolf	2014-07-31
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*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30
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*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Added techmap -extern	Clifford Wolf	2014-07-27
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*	Added topological sorting to techmap	Clifford Wolf	2014-07-27
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at\("([^"])"\)/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
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*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
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*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
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*	Added call_on_selection() and call_on_module() API	Clifford Wolf	2014-07-20
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*	Added support for "blackbox" attribute to flatten/techmap	Clifford Wolf	2014-07-17
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*	be more verbose when techmap yielded processes	Johann Glaser	2014-05-26
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*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13
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*	- kernel/register.h, kernel/driver.cc: refactor ↵	Siesh1oo	2014-03-12
\| \| \| \| \| \| \|	rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
*	Added techmap -max_iter option	Clifford Wolf	2014-03-06
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*	Added _TECHMAP_REPLACE_ feature to techmap	Clifford Wolf	2014-02-20
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*	Added techmap support for _TECHMAP_CONNMAP_*_	Clifford Wolf	2014-02-18
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*	Better preserve wires when flattening (in comparison to techmap)	Clifford Wolf	2014-02-17
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*	Added some additional checks to techmap	Clifford Wolf	2014-02-16
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*	Added CONSTMSK and CONSTVAL feature to techmap	Clifford Wolf	2014-02-16
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*	Added recursion support to techmap	Clifford Wolf	2014-02-16
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*	Changed techmap description from "simple" to "generic"	Clifford Wolf	2014-02-06
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
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*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24
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*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24
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*	Added techmap -D and -I options	Clifford Wolf	2013-11-24
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*	Added "techmap -share_map" option	Clifford Wolf	2013-11-24
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*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
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*	Fixed "flatten" top-module detection: Only use on fully selected designs	Clifford Wolf	2013-11-24
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*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24
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*	Improved handling of techmap special wires	Clifford Wolf	2013-11-23
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*	Added more generic _TECHMAP_ wire mechanism to techmap pass	Clifford Wolf	2013-11-23
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*	Call internal checker more often	Clifford Wolf	2013-11-10
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*	Improved way of connecting ports in techmap pass	Clifford Wolf	2013-10-17
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*	Added techmap -opt mode	Clifford Wolf	2013-08-09
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*	Fixed techmap/flatten for positional module arguments	Clifford Wolf	2013-05-26
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