summaryrefslogtreecommitdiff
path: root/passes/techmap/techmap.cc
Commit message (Expand)AuthorAge
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
* Improvements in simplemap api, added $ne $nex $eq $eqx supportClifford Wolf2014-12-24
* Improved TopoSort determinismClifford Wolf2014-11-07
* Added format __attribute__ to stringf()Clifford Wolf2014-10-10
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* namespace YosysClifford Wolf2014-09-27
* Fixed techmap_wrap for techmap_celltypeClifford Wolf2014-09-14
* Added techmap_wrap attributeClifford Wolf2014-09-14
* Added 'techmap_maccmap' techmap attributeClifford Wolf2014-09-07
* Added "techmap -autoproc"Clifford Wolf2014-09-01
* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-23
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
* Renamed toposort.h to utils.hClifford Wolf2014-08-17
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
* document "techmap -map %<design-name>"Clifford Wolf2014-08-15
* Implemented recursive techmapClifford Wolf2014-08-03
* Implemented simplemap support for "techmap -extern"Clifford Wolf2014-08-02
* Bugfix in "techmap -extern"Clifford Wolf2014-08-02
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Replaced sha1 implementationClifford Wolf2014-08-01
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
* Added "techmap -assert"Clifford Wolf2014-07-31
* Added techmap CONSTMAP featureClifford Wolf2014-07-30
* Added "techmap -map %{design-name}"Clifford Wolf2014-07-29
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added techmap -externClifford Wolf2014-07-27
* Added topological sorting to techmapClifford Wolf2014-07-27
* Using new obj iterator API in a few placesClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Added call_on_selection() and call_on_module() APIClifford Wolf2014-07-20
* Added support for "blackbox" attribute to flatten/techmapClifford Wolf2014-07-17
* be more verbose when techmap yielded processesJohann Glaser2014-05-26
* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
* - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...Siesh1oo2014-03-12
* Added techmap -max_iter optionClifford Wolf2014-03-06