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* Added "maccmap" commandClifford Wolf2014-09-07
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Added "techmap -autoproc"Clifford Wolf2014-09-01
* Fixed inserting of Q-inverters in dfflibmapClifford Wolf2014-08-27
* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-23
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
* Renamed toposort.h to utils.hClifford Wolf2014-08-17
* Bugfix in iopadmapClifford Wolf2014-08-15
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
* document "techmap -map %<design-name>"Clifford Wolf2014-08-15
* Added module->portsClifford Wolf2014-08-14
* Implemented recursive techmapClifford Wolf2014-08-03
* Implemented simplemap support for "techmap -extern"Clifford Wolf2014-08-02
* Bugfix in "techmap -extern"Clifford Wolf2014-08-02
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Replaced sha1 implementationClifford Wolf2014-08-01
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
* Added "techmap -assert"Clifford Wolf2014-07-31
* Added techmap CONSTMAP featureClifford Wolf2014-07-30
* Added "techmap -map %{design-name}"Clifford Wolf2014-07-29
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added techmap -externClifford Wolf2014-07-27
* Added topological sorting to techmapClifford Wolf2014-07-27
* Using new obj iterator API in a few placesClifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Added "make SMALL=1"Clifford Wolf2014-07-24
* Added "make PRETTY=1"Clifford Wolf2014-07-24
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22