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* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Added "make SMALL=1"Clifford Wolf2014-07-24
* Added "make PRETTY=1"Clifford Wolf2014-07-24
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-22
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
* Added call_on_selection() and call_on_module() APIClifford Wolf2014-07-20
* Added support for "blackbox" attribute to iopadmapClifford Wolf2014-07-17
* Added support for "blackbox" attribute to flatten/techmapClifford Wolf2014-07-17
* be more verbose when techmap yielded processesJohann Glaser2014-05-26
* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
* - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...Siesh1oo2014-03-12
* OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/...Clifford Wolf2014-03-11
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
* Fixed dumping of timing() { .. } block in libparseClifford Wolf2014-03-09
* Added techmap -max_iter optionClifford Wolf2014-03-06
* Added _TECHMAP_REPLACE_ feature to techmapClifford Wolf2014-02-20
* Added "extract -ignore_parameters" and "extract -ignore_param ..."Clifford Wolf2014-02-20
* Added "extract -map %<design_name>"Clifford Wolf2014-02-20
* Added techmap support for _TECHMAP_CONNMAP_*_Clifford Wolf2014-02-18
* Better preserve wires when flattening (in comparison to techmap)Clifford Wolf2014-02-17
* Added some additional checks to techmapClifford Wolf2014-02-16
* Added CONSTMSK and CONSTVAL feature to techmapClifford Wolf2014-02-16
* Added recursion support to techmapClifford Wolf2014-02-16
* Added iopadmap -bitsClifford Wolf2014-02-15
* Fixed dfflibmap for cell libraries with no set-reset-ffClifford Wolf2014-02-15
* Moved some passes to other source directoriesClifford Wolf2014-02-08
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Changed techmap description from "simple" to "generic"Clifford Wolf2014-02-06
* Added support for // comments in liberty parserClifford Wolf2014-01-25
* Added hilomap commandClifford Wolf2014-01-19
* renamed LibertyParer to LibertyParserClifford Wolf2014-01-14
* Added "+" to list of liberty token charactersClifford Wolf2014-01-14
* Fixed undef extend for bitwise binary ops (bugs in simplemap and satgen)Clifford Wolf2013-12-29
* Added new cell types to manualClifford Wolf2013-12-28
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-28
* Fixed dfflibmap for unused output portsClifford Wolf2013-12-21
* Now prefer smallest cells in dfflibmapClifford Wolf2013-12-21
* Cleanup of dfflibmap cellmap exploration codeClifford Wolf2013-12-20
* Further improved dfflibmap cellmap explorationClifford Wolf2013-12-20
* Fixed dfflibmap endless-loop bugClifford Wolf2013-12-20
* Prefer non-inverted clocks in dfflibmapClifford Wolf2013-12-19
* Replaced signed_parameters API with CONST_FLAG_SIGNEDClifford Wolf2013-12-04