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techmap
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Author
Age
*
Renamed toposort.h to utils.h
Clifford Wolf
2014-08-17
*
Bugfix in iopadmap
Clifford Wolf
2014-08-15
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
*
More idstring sort_by_* helpers and fixed tpl ordering in techmap
Clifford Wolf
2014-08-15
*
document "techmap -map %<design-name>"
Clifford Wolf
2014-08-15
*
Added module->ports
Clifford Wolf
2014-08-14
*
Implemented recursive techmap
Clifford Wolf
2014-08-03
*
Implemented simplemap support for "techmap -extern"
Clifford Wolf
2014-08-02
*
Bugfix in "techmap -extern"
Clifford Wolf
2014-08-02
*
No implicit conversion from IdString to anything else
Clifford Wolf
2014-08-02
*
More bugfixes related to new RTLIL::IdString
Clifford Wolf
2014-08-02
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
*
Replaced sha1 implementation
Clifford Wolf
2014-08-01
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
*
Renamed "stdcells.v" to "techmap.v"
Clifford Wolf
2014-07-31
*
Added "techmap -assert"
Clifford Wolf
2014-07-31
*
Added techmap CONSTMAP feature
Clifford Wolf
2014-07-30
*
Added "techmap -map %{design-name}"
Clifford Wolf
2014-07-29
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Added techmap -extern
Clifford Wolf
2014-07-27
*
Added topological sorting to techmap
Clifford Wolf
2014-07-27
*
Using new obj iterator API in a few places
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed more code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
More RTLIL::Cell API usage cleanups
Clifford Wolf
2014-07-26
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Added copy-constructor-like module->addCell(name, other) method
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Added "make SMALL=1"
Clifford Wolf
2014-07-24
*
Added "make PRETTY=1"
Clifford Wolf
2014-07-24
*
Removed RTLIL::SigSpec::expand() method
Clifford Wolf
2014-07-23
*
Fixed all users of SigSpec::chunks_rw() and removed it
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Clifford Wolf
2014-07-23
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
Replaced depricated NEW_WIRE macro with module->addWire() calls
Clifford Wolf
2014-07-21
*
Removed deprecated module->new_wire()
Clifford Wolf
2014-07-21
*
Added call_on_selection() and call_on_module() API
Clifford Wolf
2014-07-20
*
Added support for "blackbox" attribute to iopadmap
Clifford Wolf
2014-07-17
*
Added support for "blackbox" attribute to flatten/techmap
Clifford Wolf
2014-07-17
*
be more verbose when techmap yielded processes
Johann Glaser
2014-05-26
*
Merged OSX fixes from Siesh1oo with some modifications
Clifford Wolf
2014-03-13
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