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* Added $dffe cell typeClifford Wolf2014-12-08
* Improved TopoSort determinismClifford Wolf2014-11-07
* Fixed various VS warningsClifford Wolf2014-10-18
* Added genfiles.zip to MXE "make dist"Clifford Wolf2014-10-17
* Removed CHECK() macro from libparse.cc (was using non-std c features)Clifford Wolf2014-10-13
* More Win32 build fixesClifford Wolf2014-10-10
* Added format __attribute__ to stringf()Clifford Wolf2014-10-10
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-10
* Added mxe-based cross build for win32Clifford Wolf2014-10-09
* Fixes in "hilomap" help messageClifford Wolf2014-10-08
* namespace YosysClifford Wolf2014-09-27
* More aggressive $macc merging in alumaccClifford Wolf2014-09-15
* Added the obvious optimizations to alumacc $macc generatorClifford Wolf2014-09-15
* Improved maccmap tree bit packingClifford Wolf2014-09-15
* Fixed techmap_wrap for techmap_celltypeClifford Wolf2014-09-14
* Various fixes/cleanups in alumacc and maccmapClifford Wolf2014-09-14
* Added techmap_wrap attributeClifford Wolf2014-09-14
* alumacc fix for $pos cellsClifford Wolf2014-09-14
* Extract $alu cells in alumaccClifford Wolf2014-09-14
* Merge $macc cells in alumacc passClifford Wolf2014-09-14
* Basic $macc extract in alumaccClifford Wolf2014-09-14
* alumacc skeletonClifford Wolf2014-09-14
* Added "$fa" cell typeClifford Wolf2014-09-08
* Trim msb/lsb zero bits from full adder in maccmapClifford Wolf2014-09-08
* Added 'techmap_maccmap' techmap attributeClifford Wolf2014-09-07
* Added "maccmap" commandClifford Wolf2014-09-07
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Added "techmap -autoproc"Clifford Wolf2014-09-01
* Fixed inserting of Q-inverters in dfflibmapClifford Wolf2014-08-27
* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-23
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
* Renamed toposort.h to utils.hClifford Wolf2014-08-17
* Bugfix in iopadmapClifford Wolf2014-08-15
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
* document "techmap -map %<design-name>"Clifford Wolf2014-08-15
* Added module->portsClifford Wolf2014-08-14
* Implemented recursive techmapClifford Wolf2014-08-03
* Implemented simplemap support for "techmap -extern"Clifford Wolf2014-08-02
* Bugfix in "techmap -extern"Clifford Wolf2014-08-02
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Replaced sha1 implementationClifford Wolf2014-08-01
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
* Added "techmap -assert"Clifford Wolf2014-07-31