yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added sat -max_undef feature	Clifford Wolf	2013-12-07
*	Added "sat" undef support and "sat -set-init" options	Clifford Wolf	2013-12-07
*	Fixed compiler warining in passes/sat/eval.cc	Clifford Wolf	2013-12-07
*	Added eval -set-undef and eval -table	Clifford Wolf	2013-12-07
*	Fixes in fsm detect/extract for better detection of non-fsm circuits	Clifford Wolf	2013-12-06
*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Fixed submod for non-primitive cells	Clifford Wolf	2013-12-02
*	Fixed submod for non-cleaned designs	Clifford Wolf	2013-12-02
*	A fix in memory_dff for write ports with static addresses	Clifford Wolf	2013-12-01
*	Progress on AppNote 011	Clifford Wolf	2013-11-29
*	Added pattern support to "ls" command	Clifford Wolf	2013-11-28
*	Improved ID matching scheme in select (and thus for all commands)	Clifford Wolf	2013-11-28
*	Fixes and improvements in "show" command	Clifford Wolf	2013-11-28
*	Added "src" attribute to processes	Clifford Wolf	2013-11-28
*	Added support for "show -pause" and "show -format dot"	Clifford Wolf	2013-11-28
*	Tighter integration of ABC build	Clifford Wolf	2013-11-27
*	Started implementing undef support in "sat" command	Clifford Wolf	2013-11-25
*	Bugfixes in new "stat" command	Clifford Wolf	2013-11-25
*	Added "stat" command	Clifford Wolf	2013-11-25
*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25
*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25
*	Started implementing undef handling in satgen	Clifford Wolf	2013-11-25
*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24
*	Added simplemap pass	Clifford Wolf	2013-11-24
*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24
*	Added techmap -D and -I options	Clifford Wolf	2013-11-24
*	Added "techmap -share_map" option	Clifford Wolf	2013-11-24
*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
*	Fixed "flatten" top-module detection: Only use on fully selected designs	Clifford Wolf	2013-11-24
*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24
*	Improved handling of techmap special wires	Clifford Wolf	2013-11-23
*	Added more generic _TECHMAP_ wire mechanism to techmap pass	Clifford Wolf	2013-11-23
*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
*	Updated abc	Clifford Wolf	2013-11-21
*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
*	Fixed a bug in "add -global_input"	Clifford Wolf	2013-11-21
*	Added "proc_arst -global_arst" feature	Clifford Wolf	2013-11-20
*	Added "add" command (only wires for now)	Clifford Wolf	2013-11-20
*	Renamed temp module generated by "abc" pass from "logic" to "netlist"	Clifford Wolf	2013-11-19
*	Fixed abc pass blif parser for constant bits	Clifford Wolf	2013-11-13
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11
*	Call internal checker more often	Clifford Wolf	2013-11-10
*	Improved user-friendliness of "sat" and "eval" expression parsing	Clifford Wolf	2013-11-09
*	Added verification of SAT model to "eval -vloghammer_report" command	Clifford Wolf	2013-11-09
*	Fixed keep attribute on wires in opt_clean	Clifford Wolf	2013-11-08
*	Renamed extend_un0() to extend_u0() and use it in genrtlil	Clifford Wolf	2013-11-07
*	Fixed type of sign extension in opt_const $eq/$ne handling	Clifford Wolf	2013-11-07
*	Fixed $eq/$ne bitwise optimization in opt_const	Clifford Wolf	2013-11-07