path: root/passes
Commit message (Expand)AuthorAge
* Small improvement in SAT log messagesClifford Wolf2014-03-13
* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
* - kernel/register.h, kernel/ refactor rewrite_yosys_exe()/get_shar...Siesh1oo2014-03-12
* OSX compatible creation of, using code from Wolf2014-03-11
* Merged a few fixes for non-posix systems from Wolf2014-03-11
* Fixed memory corruption in passes/abc/blifparse.ccClifford Wolf2014-03-11
* Fixed dumping of timing() { .. } block in libparseClifford Wolf2014-03-09
* Verbose reading of liberty and constr files in ABC passClifford Wolf2014-03-09
* Fixed bug in freduce commandClifford Wolf2014-03-07
* Some minor code cleanups in freduce commandClifford Wolf2014-03-07
* Added freduce -dumpClifford Wolf2014-03-06
* Added freduce -stopClifford Wolf2014-03-06
* Fixed undef handling in opt_reduceClifford Wolf2014-03-06
* Added techmap -max_iter optionClifford Wolf2014-03-06
* fixed freduce for Minisat::SimpSolver: use frozen_literal()Clifford Wolf2014-03-03
* Fixed const folding of $bu0 cellsClifford Wolf2014-02-27
* Fixed bug (typo) in passes/opt/opt_const.ccClifford Wolf2014-02-22
* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-21
* Added _TECHMAP_REPLACE_ feature to techmapClifford Wolf2014-02-20
* Added "extract -ignore_parameters" and "extract -ignore_param ..."Clifford Wolf2014-02-20
* Added "extract -map %<design_name>"Clifford Wolf2014-02-20
* Added "design -push" and "design -pop"Clifford Wolf2014-02-20
* Added connwrappers commandClifford Wolf2014-02-20
* Merge branch 'master' of Wolf2014-02-18
| * Added "sat -dump_cnf"Clifford Wolf2014-02-18
| * Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-18
| * Added "sat -initsteps"Clifford Wolf2014-02-18
* | Added techmap support for _TECHMAP_CONNMAP_*_Clifford Wolf2014-02-18
* Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanupsClifford Wolf2014-02-17
* Added "-dump_fail_to_vcd" argument to SAT solverAndrew Zonenberg2014-02-17
* Better preserve wires when flattening (in comparison to techmap)Clifford Wolf2014-02-17
* Added some additional checks to techmapClifford Wolf2014-02-16
* Added CONSTMSK and CONSTVAL feature to techmapClifford Wolf2014-02-16
* Fixed handling of "keep" attribute on wires in opt_cleanClifford Wolf2014-02-16
* Fixed use of selection in splitnets commandClifford Wolf2014-02-16
* Added recursion support to techmapClifford Wolf2014-02-16
* Added != support for relational select patternClifford Wolf2014-02-16
* Added iopadmap -bitsClifford Wolf2014-02-15
* Fixed dfflibmap for cell libraries with no set-reset-ffClifford Wolf2014-02-15
* Fixed opt_const handling of double invert with non-1 output widthClifford Wolf2014-02-15
* Added abc -keepff optionClifford Wolf2014-02-14
* updated default ABC command stringsClifford Wolf2014-02-13
* Updated ABCClifford Wolf2014-02-13
* Implemented read_verilog -deferClifford Wolf2014-02-13
* Removed double blanks in ABC default command sequencesClifford Wolf2014-02-13
* Updated ABC and some related changesClifford Wolf2014-02-13
* Updated ABC to rev e97a6e1d59b9Clifford Wolf2014-02-12
* Various improvements in expose command (added -sep and -cut)Clifford Wolf2014-02-09
* Added delete {-input|-output|-port}Clifford Wolf2014-02-09
* Bugfix in delete commandClifford Wolf2014-02-09