summaryrefslogtreecommitdiff
path: root/passes
Commit message (Collapse)AuthorAge
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
|
* Added "techmap -assert"Clifford Wolf2014-07-31
|
* Added techmap CONSTMAP featureClifford Wolf2014-07-30
|
* Added write_file commandClifford Wolf2014-07-30
|
* Improvements in test_cellClifford Wolf2014-07-30
|
* Added "test_cell" commandClifford Wolf2014-07-29
|
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-29
|
* Allow "hierarchy -generate" for $__ cellsClifford Wolf2014-07-29
|
* Added "techmap -map %{design-name}"Clifford Wolf2014-07-29
|
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
|
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
|
* Added techmap -externClifford Wolf2014-07-27
|
* Added topological sorting to techmapClifford Wolf2014-07-27
|
* Added SigPool::check(bit)Clifford Wolf2014-07-27
|
* Fixed bug in opt_cleanClifford Wolf2014-07-27
|
* Improved performance of opt_const on large modulesClifford Wolf2014-07-27
|
* Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-27
|
* Added log_cmd_error_expectionClifford Wolf2014-07-27
|
* Using new obj iterator API in a few placesClifford Wolf2014-07-27
|
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
|
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
|
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
|
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
|
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
|
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
|
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
|
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
|
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
|
* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
|
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
|
* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
|
* Fixed memory corruption in "opt_reduce" passClifford Wolf2014-07-25
|
* Disabled cover() for non-linux buildsClifford Wolf2014-07-25
|
* Improvements in "cover" commandClifford Wolf2014-07-25
|
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
|
* Added cover() calls to opt_constClifford Wolf2014-07-24
|
* Added "make SMALL=1"Clifford Wolf2014-07-24
|
* Added "make PRETTY=1"Clifford Wolf2014-07-24
|
* Added "cover" commandClifford Wolf2014-07-24
|
* Various small fixes (from gcc compiler warnings)Clifford Wolf2014-07-23
|
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
|
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
|
* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
|
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
|
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
|
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-23
|
* SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commandsClifford Wolf2014-07-22
|
* Fixed memory corruption with new SigSpec API in proc_muxClifford Wolf2014-07-22
|
* fixed memory leak in fsm_optClifford Wolf2014-07-22
|