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Commit message (
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Author
Age
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Tighter integration of ABC build
Clifford Wolf
2013-11-27
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Started implementing undef support in "sat" command
Clifford Wolf
2013-11-25
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Bugfixes in new "stat" command
Clifford Wolf
2013-11-25
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Added "stat" command
Clifford Wolf
2013-11-25
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Improvements in satgen undef handling
Clifford Wolf
2013-11-25
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Improvements in satgen undef handling
Clifford Wolf
2013-11-25
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Started implementing undef handling in satgen
Clifford Wolf
2013-11-25
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Using simplemap mappers from techmap
Clifford Wolf
2013-11-24
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Added simplemap pass
Clifford Wolf
2013-11-24
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Added module->avail_parameters (for advanced techmap features)
Clifford Wolf
2013-11-24
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Added techmap -D and -I options
Clifford Wolf
2013-11-24
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Added "techmap -share_map" option
Clifford Wolf
2013-11-24
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Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
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Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
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Fixed "flatten" top-module detection: Only use on fully selected designs
Clifford Wolf
2013-11-24
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Added "top" attribute to mark top module in hierarchy
Clifford Wolf
2013-11-24
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Improved handling of techmap special wires
Clifford Wolf
2013-11-23
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Added more generic _TECHMAP_ wire mechanism to techmap pass
Clifford Wolf
2013-11-23
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Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
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Updated abc
Clifford Wolf
2013-11-21
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Major improvements in mem2reg and added "init" sync rules
Clifford Wolf
2013-11-21
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Fixed a bug in "add -global_input"
Clifford Wolf
2013-11-21
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Added "proc_arst -global_arst" feature
Clifford Wolf
2013-11-20
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Added "add" command (only wires for now)
Clifford Wolf
2013-11-20
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Renamed temp module generated by "abc" pass from "logic" to "netlist"
Clifford Wolf
2013-11-19
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Fixed abc pass blif parser for constant bits
Clifford Wolf
2013-11-13
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Cleanups and bugfixes in response to new internal cell checker
Clifford Wolf
2013-11-11
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Call internal checker more often
Clifford Wolf
2013-11-10
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Improved user-friendliness of "sat" and "eval" expression parsing
Clifford Wolf
2013-11-09
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Added verification of SAT model to "eval -vloghammer_report" command
Clifford Wolf
2013-11-09
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Fixed keep attribute on wires in opt_clean
Clifford Wolf
2013-11-08
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Renamed extend_un0() to extend_u0() and use it in genrtlil
Clifford Wolf
2013-11-07
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Fixed type of sign extension in opt_const $eq/$ne handling
Clifford Wolf
2013-11-07
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Fixed $eq/$ne bitwise optimization in opt_const
Clifford Wolf
2013-11-07
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Added handling of unconnected/unspecified signals to eval -vloghammer_report
Clifford Wolf
2013-11-06
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Added correct RTL undef handling to eval vloghammer mode
Clifford Wolf
2013-11-06
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Added eval -vloghammer_report mode
Clifford Wolf
2013-11-06
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Added support for "keep" attributes on wires
Clifford Wolf
2013-11-05
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2013-11-03
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Added resolution of positional arguments to hierarchy pass
Clifford Wolf
2013-11-03
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Added placeholder check to dfflibmap and cleaned up some other placeholder ch...
Clifford Wolf
2013-10-31
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Added detection for endless recursion in fsm_detect pass
Clifford Wolf
2013-10-30
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Fixed help message typo (memory pass)
Clifford Wolf
2013-10-30
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Added -format option to splitnets
Clifford Wolf
2013-10-29
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Added support for i/o buffers to iopadmap
Clifford Wolf
2013-10-26
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Added support for sr flip-flops to dfflibmap
Clifford Wolf
2013-10-24
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Added support for complex set-reset flip-flops in proc_dff
Clifford Wolf
2013-10-24
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Fixed handling of boolean attributes (passes)
Clifford Wolf
2013-10-24
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Improved handling of dff with async resets
Clifford Wolf
2013-10-21
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Added handling of multiple async paths in proc_arst
Clifford Wolf
2013-10-19
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