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* Added %D and %c select commandsClifford Wolf2014-06-14
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* fixed cell array handling of positional argumentsClifford Wolf2014-06-07
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* Add support for cell arraysClifford Wolf2014-06-07
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* added tee cmdClifford Wolf2014-06-03
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* Fixed log messages in memory_dffClifford Wolf2014-06-01
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* added log_header to miter and expose pass, show cell type for exposed portsJohann Glaser2014-05-28
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* be more verbose when techmap yielded processesJohann Glaser2014-05-26
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* Fixed bug in opt_reduce (see vloghammer issue_044)Clifford Wolf2014-05-12
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* fixed syntax error in dot file created by "show" commandClifford Wolf2014-05-10
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* Fixed performance problem in opt_mux with nets driven by many conflicting ↵Clifford Wolf2014-03-19
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* Small improvement in SAT log messagesClifford Wolf2014-03-13
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* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
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* - kernel/register.h, kernel/driver.cc: refactor ↵Siesh1oo2014-03-12
| | | | | | | rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
* OSX compatible creation of stdcells.inc, using code from ↵Clifford Wolf2014-03-11
| | | | | | github.com/Siesh1oo/yosys (see https://github.com/cliffordwolf/yosys/pull/28)
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
| | | | (see https://github.com/cliffordwolf/yosys/pull/28)
* Fixed memory corruption in passes/abc/blifparse.ccClifford Wolf2014-03-11
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* Fixed dumping of timing() { .. } block in libparseClifford Wolf2014-03-09
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* Verbose reading of liberty and constr files in ABC passClifford Wolf2014-03-09
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* Fixed bug in freduce commandClifford Wolf2014-03-07
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* Some minor code cleanups in freduce commandClifford Wolf2014-03-07
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* Added freduce -dumpClifford Wolf2014-03-06
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* Added freduce -stopClifford Wolf2014-03-06
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* Fixed undef handling in opt_reduceClifford Wolf2014-03-06
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* Added techmap -max_iter optionClifford Wolf2014-03-06
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* fixed freduce for Minisat::SimpSolver: use frozen_literal()Clifford Wolf2014-03-03
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* Fixed const folding of $bu0 cellsClifford Wolf2014-02-27
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* Fixed bug (typo) in passes/opt/opt_const.ccClifford Wolf2014-02-22
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* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-21
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* Added _TECHMAP_REPLACE_ feature to techmapClifford Wolf2014-02-20
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* Added "extract -ignore_parameters" and "extract -ignore_param ..."Clifford Wolf2014-02-20
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* Added "extract -map %<design_name>"Clifford Wolf2014-02-20
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* Added "design -push" and "design -pop"Clifford Wolf2014-02-20
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* Added connwrappers commandClifford Wolf2014-02-20
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-18
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| * Added "sat -dump_cnf"Clifford Wolf2014-02-18
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| * Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-18
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| * Added "sat -initsteps"Clifford Wolf2014-02-18
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* | Added techmap support for _TECHMAP_CONNMAP_*_Clifford Wolf2014-02-18
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* Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanupsClifford Wolf2014-02-17
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* Added "-dump_fail_to_vcd" argument to SAT solverAndrew Zonenberg2014-02-17
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* Better preserve wires when flattening (in comparison to techmap)Clifford Wolf2014-02-17
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* Added some additional checks to techmapClifford Wolf2014-02-16
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* Added CONSTMSK and CONSTVAL feature to techmapClifford Wolf2014-02-16
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* Fixed handling of "keep" attribute on wires in opt_cleanClifford Wolf2014-02-16
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* Fixed use of selection in splitnets commandClifford Wolf2014-02-16
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* Added recursion support to techmapClifford Wolf2014-02-16
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* Added != support for relational select patternClifford Wolf2014-02-16
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* Added iopadmap -bitsClifford Wolf2014-02-15
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* Fixed dfflibmap for cell libraries with no set-reset-ffClifford Wolf2014-02-15
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* Fixed opt_const handling of double invert with non-1 output widthClifford Wolf2014-02-15
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