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* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-21
* Added _TECHMAP_REPLACE_ feature to techmapClifford Wolf2014-02-20
* Added "extract -ignore_parameters" and "extract -ignore_param ..."Clifford Wolf2014-02-20
* Added "extract -map %<design_name>"Clifford Wolf2014-02-20
* Added "design -push" and "design -pop"Clifford Wolf2014-02-20
* Added connwrappers commandClifford Wolf2014-02-20
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-18
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| * Added "sat -dump_cnf"Clifford Wolf2014-02-18
| * Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-18
| * Added "sat -initsteps"Clifford Wolf2014-02-18
* | Added techmap support for _TECHMAP_CONNMAP_*_Clifford Wolf2014-02-18
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* Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanupsClifford Wolf2014-02-17
* Added "-dump_fail_to_vcd" argument to SAT solverAndrew Zonenberg2014-02-17
* Better preserve wires when flattening (in comparison to techmap)Clifford Wolf2014-02-17
* Added some additional checks to techmapClifford Wolf2014-02-16
* Added CONSTMSK and CONSTVAL feature to techmapClifford Wolf2014-02-16
* Fixed handling of "keep" attribute on wires in opt_cleanClifford Wolf2014-02-16
* Fixed use of selection in splitnets commandClifford Wolf2014-02-16
* Added recursion support to techmapClifford Wolf2014-02-16
* Added != support for relational select patternClifford Wolf2014-02-16
* Added iopadmap -bitsClifford Wolf2014-02-15
* Fixed dfflibmap for cell libraries with no set-reset-ffClifford Wolf2014-02-15
* Fixed opt_const handling of double invert with non-1 output widthClifford Wolf2014-02-15
* Added abc -keepff optionClifford Wolf2014-02-14
* updated default ABC command stringsClifford Wolf2014-02-13
* Updated ABCClifford Wolf2014-02-13
* Implemented read_verilog -deferClifford Wolf2014-02-13
* Removed double blanks in ABC default command sequencesClifford Wolf2014-02-13
* Updated ABC and some related changesClifford Wolf2014-02-13
* Updated ABC to rev e97a6e1d59b9Clifford Wolf2014-02-12
* Various improvements in expose command (added -sep and -cut)Clifford Wolf2014-02-09
* Added delete {-input|-output|-port}Clifford Wolf2014-02-09
* Bugfix in delete commandClifford Wolf2014-02-09
* Fixed handling of async reset in expose -evert-dffClifford Wolf2014-02-08
* Build fixes for log cmdClifford Wolf2014-02-08
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-08
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| * added "log" commandJohann Glaser2014-02-08
* | Implemented expose -evert-dffClifford Wolf2014-02-08
* | Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collectClifford Wolf2014-02-08
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* Added various new options to splice commandClifford Wolf2014-02-08
* Added %a select operatorClifford Wolf2014-02-08
* Moved some passes to other source directoriesClifford Wolf2014-02-08
* Added support for "keep" attribute to abc passClifford Wolf2014-02-08
* Added opt -purge (frontend to opt_clean -purge)Clifford Wolf2014-02-08
* Only count non-trivial attributes when findinf master signal in opt_cleanClifford Wolf2014-02-08
* Now also move net labes to the right position in splice cmdClifford Wolf2014-02-08
* Improved detection of primary wire for a signal in opt_cleanClifford Wolf2014-02-07
* Added splice commandClifford Wolf2014-02-07
* Added log_header() to splitnetsClifford Wolf2014-02-07
* Added $slice and $concat cell typesClifford Wolf2014-02-07