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Author
Age
*
Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst
Clifford Wolf
2014-02-21
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Added _TECHMAP_REPLACE_ feature to techmap
Clifford Wolf
2014-02-20
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Added "extract -ignore_parameters" and "extract -ignore_param ..."
Clifford Wolf
2014-02-20
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Added "extract -map %<design_name>"
Clifford Wolf
2014-02-20
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Added "design -push" and "design -pop"
Clifford Wolf
2014-02-20
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Added connwrappers command
Clifford Wolf
2014-02-20
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2014-02-18
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Added "sat -dump_cnf"
Clifford Wolf
2014-02-18
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Coding style corrections in SatHelper::dump_model_to_vcd()
Clifford Wolf
2014-02-18
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Added "sat -initsteps"
Clifford Wolf
2014-02-18
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Added techmap support for _TECHMAP_CONNMAP_*_
Clifford Wolf
2014-02-18
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Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups
Clifford Wolf
2014-02-17
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Added "-dump_fail_to_vcd" argument to SAT solver
Andrew Zonenberg
2014-02-17
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Better preserve wires when flattening (in comparison to techmap)
Clifford Wolf
2014-02-17
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Added some additional checks to techmap
Clifford Wolf
2014-02-16
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Added CONSTMSK and CONSTVAL feature to techmap
Clifford Wolf
2014-02-16
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Fixed handling of "keep" attribute on wires in opt_clean
Clifford Wolf
2014-02-16
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Fixed use of selection in splitnets command
Clifford Wolf
2014-02-16
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Added recursion support to techmap
Clifford Wolf
2014-02-16
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Added != support for relational select pattern
Clifford Wolf
2014-02-16
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Added iopadmap -bits
Clifford Wolf
2014-02-15
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Fixed dfflibmap for cell libraries with no set-reset-ff
Clifford Wolf
2014-02-15
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Fixed opt_const handling of double invert with non-1 output width
Clifford Wolf
2014-02-15
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Added abc -keepff option
Clifford Wolf
2014-02-14
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updated default ABC command strings
Clifford Wolf
2014-02-13
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Updated ABC
Clifford Wolf
2014-02-13
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Implemented read_verilog -defer
Clifford Wolf
2014-02-13
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Removed double blanks in ABC default command sequences
Clifford Wolf
2014-02-13
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Updated ABC and some related changes
Clifford Wolf
2014-02-13
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Updated ABC to rev e97a6e1d59b9
Clifford Wolf
2014-02-12
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Various improvements in expose command (added -sep and -cut)
Clifford Wolf
2014-02-09
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Added delete {-input|-output|-port}
Clifford Wolf
2014-02-09
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Bugfix in delete command
Clifford Wolf
2014-02-09
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Fixed handling of async reset in expose -evert-dff
Clifford Wolf
2014-02-08
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Build fixes for log cmd
Clifford Wolf
2014-02-08
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2014-02-08
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added "log" command
Johann Glaser
2014-02-08
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Implemented expose -evert-dff
Clifford Wolf
2014-02-08
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Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
Clifford Wolf
2014-02-08
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Added various new options to splice command
Clifford Wolf
2014-02-08
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Added %a select operator
Clifford Wolf
2014-02-08
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Moved some passes to other source directories
Clifford Wolf
2014-02-08
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Added support for "keep" attribute to abc pass
Clifford Wolf
2014-02-08
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Added opt -purge (frontend to opt_clean -purge)
Clifford Wolf
2014-02-08
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Only count non-trivial attributes when findinf master signal in opt_clean
Clifford Wolf
2014-02-08
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Now also move net labes to the right position in splice cmd
Clifford Wolf
2014-02-08
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Improved detection of primary wire for a signal in opt_clean
Clifford Wolf
2014-02-07
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Added splice command
Clifford Wolf
2014-02-07
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Added log_header() to splitnets
Clifford Wolf
2014-02-07
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Added $slice and $concat cell types
Clifford Wolf
2014-02-07
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