yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
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*	Added sat -set-def/-set-*-undef support	Clifford Wolf	2013-12-27
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*	Renamed sat -set-undef to -set-any-undef	Clifford Wolf	2013-12-27
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*	Fixed dfflibmap for unused output ports	Clifford Wolf	2013-12-21
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*	Now prefer smallest cells in dfflibmap	Clifford Wolf	2013-12-21
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*	Cleanup of dfflibmap cellmap exploration code	Clifford Wolf	2013-12-20
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*	Further improved dfflibmap cellmap exploration	Clifford Wolf	2013-12-20
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*	Fixed dfflibmap endless-loop bug	Clifford Wolf	2013-12-20
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*	Prefer non-inverted clocks in dfflibmap	Clifford Wolf	2013-12-19
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*	Added sat -max_undef feature	Clifford Wolf	2013-12-07
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*	Added "sat" undef support and "sat -set-init" options	Clifford Wolf	2013-12-07
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*	Fixed compiler warining in passes/sat/eval.cc	Clifford Wolf	2013-12-07
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*	Added eval -set-undef and eval -table	Clifford Wolf	2013-12-07
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*	Fixes in fsm detect/extract for better detection of non-fsm circuits	Clifford Wolf	2013-12-06
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
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*	Fixed submod for non-primitive cells	Clifford Wolf	2013-12-02
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*	Fixed submod for non-cleaned designs	Clifford Wolf	2013-12-02
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*	A fix in memory_dff for write ports with static addresses	Clifford Wolf	2013-12-01
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*	Progress on AppNote 011	Clifford Wolf	2013-11-29
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*	Added pattern support to "ls" command	Clifford Wolf	2013-11-28
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*	Improved ID matching scheme in select (and thus for all commands)	Clifford Wolf	2013-11-28
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*	Fixes and improvements in "show" command	Clifford Wolf	2013-11-28
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*	Added "src" attribute to processes	Clifford Wolf	2013-11-28
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*	Added support for "show -pause" and "show -format dot"	Clifford Wolf	2013-11-28
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*	Tighter integration of ABC build	Clifford Wolf	2013-11-27
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*	Started implementing undef support in "sat" command	Clifford Wolf	2013-11-25
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*	Bugfixes in new "stat" command	Clifford Wolf	2013-11-25
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*	Added "stat" command	Clifford Wolf	2013-11-25
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*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25
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*	Improvements in satgen undef handling	Clifford Wolf	2013-11-25
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*	Started implementing undef handling in satgen	Clifford Wolf	2013-11-25
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*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24
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*	Added simplemap pass	Clifford Wolf	2013-11-24
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*	Added module->avail_parameters (for advanced techmap features)	Clifford Wolf	2013-11-24
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*	Added techmap -D and -I options	Clifford Wolf	2013-11-24
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*	Added "techmap -share_map" option	Clifford Wolf	2013-11-24
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*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
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*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
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*	Fixed "flatten" top-module detection: Only use on fully selected designs	Clifford Wolf	2013-11-24
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*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24
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*	Improved handling of techmap special wires	Clifford Wolf	2013-11-23
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*	Added more generic _TECHMAP_ wire mechanism to techmap pass	Clifford Wolf	2013-11-23
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
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*	Updated abc	Clifford Wolf	2013-11-21
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*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21
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*	Fixed a bug in "add -global_input"	Clifford Wolf	2013-11-21
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*	Added "proc_arst -global_arst" feature	Clifford Wolf	2013-11-20
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*	Added "add" command (only wires for now)	Clifford Wolf	2013-11-20
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*	Renamed temp module generated by "abc" pass from "logic" to "netlist"	Clifford Wolf	2013-11-19
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