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* OSX compatible creation of stdcells.inc, using code from ↵Clifford Wolf2014-03-11
| | | | | | github.com/Siesh1oo/yosys (see https://github.com/cliffordwolf/yosys/pull/28)
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
| | | | (see https://github.com/cliffordwolf/yosys/pull/28)
* Fixed memory corruption in passes/abc/blifparse.ccClifford Wolf2014-03-11
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* Fixed dumping of timing() { .. } block in libparseClifford Wolf2014-03-09
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* Verbose reading of liberty and constr files in ABC passClifford Wolf2014-03-09
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* Fixed bug in freduce commandClifford Wolf2014-03-07
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* Some minor code cleanups in freduce commandClifford Wolf2014-03-07
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* Added freduce -dumpClifford Wolf2014-03-06
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* Added freduce -stopClifford Wolf2014-03-06
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* Fixed undef handling in opt_reduceClifford Wolf2014-03-06
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* Added techmap -max_iter optionClifford Wolf2014-03-06
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* fixed freduce for Minisat::SimpSolver: use frozen_literal()Clifford Wolf2014-03-03
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* Fixed const folding of $bu0 cellsClifford Wolf2014-02-27
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* Fixed bug (typo) in passes/opt/opt_const.ccClifford Wolf2014-02-22
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* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-21
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* Added _TECHMAP_REPLACE_ feature to techmapClifford Wolf2014-02-20
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* Added "extract -ignore_parameters" and "extract -ignore_param ..."Clifford Wolf2014-02-20
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* Added "extract -map %<design_name>"Clifford Wolf2014-02-20
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* Added "design -push" and "design -pop"Clifford Wolf2014-02-20
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* Added connwrappers commandClifford Wolf2014-02-20
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-18
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| * Added "sat -dump_cnf"Clifford Wolf2014-02-18
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| * Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-18
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| * Added "sat -initsteps"Clifford Wolf2014-02-18
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* | Added techmap support for _TECHMAP_CONNMAP_*_Clifford Wolf2014-02-18
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* Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanupsClifford Wolf2014-02-17
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* Added "-dump_fail_to_vcd" argument to SAT solverAndrew Zonenberg2014-02-17
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* Better preserve wires when flattening (in comparison to techmap)Clifford Wolf2014-02-17
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* Added some additional checks to techmapClifford Wolf2014-02-16
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* Added CONSTMSK and CONSTVAL feature to techmapClifford Wolf2014-02-16
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* Fixed handling of "keep" attribute on wires in opt_cleanClifford Wolf2014-02-16
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* Fixed use of selection in splitnets commandClifford Wolf2014-02-16
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* Added recursion support to techmapClifford Wolf2014-02-16
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* Added != support for relational select patternClifford Wolf2014-02-16
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* Added iopadmap -bitsClifford Wolf2014-02-15
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* Fixed dfflibmap for cell libraries with no set-reset-ffClifford Wolf2014-02-15
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* Fixed opt_const handling of double invert with non-1 output widthClifford Wolf2014-02-15
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* Added abc -keepff optionClifford Wolf2014-02-14
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* updated default ABC command stringsClifford Wolf2014-02-13
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* Updated ABCClifford Wolf2014-02-13
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* Implemented read_verilog -deferClifford Wolf2014-02-13
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* Removed double blanks in ABC default command sequencesClifford Wolf2014-02-13
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* Updated ABC and some related changesClifford Wolf2014-02-13
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* Updated ABC to rev e97a6e1d59b9Clifford Wolf2014-02-12
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* Various improvements in expose command (added -sep and -cut)Clifford Wolf2014-02-09
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* Added delete {-input|-output|-port}Clifford Wolf2014-02-09
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* Bugfix in delete commandClifford Wolf2014-02-09
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* Fixed handling of async reset in expose -evert-dffClifford Wolf2014-02-08
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* Build fixes for log cmdClifford Wolf2014-02-08
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-08
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