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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
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* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
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* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
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* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
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* Manual fixes for new cell connections APIClifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
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* Various RTLIL::SigSpec related code cleanupsClifford Wolf2014-07-25
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* Fixed memory corruption in "opt_reduce" passClifford Wolf2014-07-25
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* Disabled cover() for non-linux buildsClifford Wolf2014-07-25
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* Improvements in "cover" commandClifford Wolf2014-07-25
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* Replaced more old SigChunk programming patternsClifford Wolf2014-07-24
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* Added cover() calls to opt_constClifford Wolf2014-07-24
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* Added "make SMALL=1"Clifford Wolf2014-07-24
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* Added "make PRETTY=1"Clifford Wolf2014-07-24
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* Added "cover" commandClifford Wolf2014-07-24
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* Various small fixes (from gcc compiler warnings)Clifford Wolf2014-07-23
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* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
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* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
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* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3Clifford Wolf2014-07-23
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* SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commandsClifford Wolf2014-07-22
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* Fixed memory corruption with new SigSpec API in proc_muxClifford Wolf2014-07-22
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* fixed memory leak in fsm_optClifford Wolf2014-07-22
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-22
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* Added "opt_const -keepdc"Clifford Wolf2014-07-21
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* Added mul to mux conversion to "opt_const -fine"Clifford Wolf2014-07-21
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* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-21
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* Added opt_const support for simple identitiesClifford Wolf2014-07-21
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* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
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* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
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* Wider range of cell types supported in "share" passClifford Wolf2014-07-21
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* Use ezSAT::non_incremental() in "share" passClifford Wolf2014-07-21
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* Added support for resource sharing in mux control logicClifford Wolf2014-07-20
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* Added "select -assert-count"Clifford Wolf2014-07-20
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* Supercell creation for $div/$mod worked all along, fixed test benchesClifford Wolf2014-07-20
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* Fixed creation of shift supercells in "share" passClifford Wolf2014-07-20
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* Added "miter -equiv -flatten"Clifford Wolf2014-07-20
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* Added call_on_selection() and call_on_module() APIClifford Wolf2014-07-20
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* Added "share" supercell creationClifford Wolf2014-07-20
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* Added removing of always inactive cells to "share" passClifford Wolf2014-07-20
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* Progress in "share" passClifford Wolf2014-07-20
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