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* Added correct RTL undef handling to eval vloghammer modeClifford Wolf2013-11-06
* Added eval -vloghammer_report modeClifford Wolf2013-11-06
* Added support for "keep" attributes on wiresClifford Wolf2013-11-05
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-11-03
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| * Added resolution of positional arguments to hierarchy passClifford Wolf2013-11-03
* | Added placeholder check to dfflibmap and cleaned up some other placeholder ch...Clifford Wolf2013-10-31
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* Added detection for endless recursion in fsm_detect passClifford Wolf2013-10-30
* Fixed help message typo (memory pass)Clifford Wolf2013-10-30
* Added -format option to splitnetsClifford Wolf2013-10-29
* Added support for i/o buffers to iopadmapClifford Wolf2013-10-26
* Added support for sr flip-flops to dfflibmapClifford Wolf2013-10-24
* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-24
* Fixed handling of boolean attributes (passes)Clifford Wolf2013-10-24
* Improved handling of dff with async resetsClifford Wolf2013-10-21
* Added handling of multiple async paths in proc_arstClifford Wolf2013-10-19
* Added dffsr support to proc_dff passClifford Wolf2013-10-18
* Improved way of connecting ports in techmap passClifford Wolf2013-10-17
* Only prefer connected signals iff they have public namesClifford Wolf2013-10-17
* Fixed bug in synthesis of memories that are never writtenClifford Wolf2013-10-17
* Avoid re-arranging signals on register outputsClifford Wolf2013-10-17
* Fixed detection of major wires in opt_cleanClifford Wolf2013-10-17
* Added iopadmap passClifford Wolf2013-10-16
* Moved dfflibmap from passes/dfflibmap to passes/techmapClifford Wolf2013-10-16
* Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";'Clifford Wolf2013-10-16
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
* Some minor documentation fixesClifford Wolf2013-08-21
* Minor fixes in abc build instructions and abc passClifford Wolf2013-08-20
* Added sat -ignore_div_by_zero switchClifford Wolf2013-08-15
* Added eval -brute_force_equiv_checker_x modeClifford Wolf2013-08-15
* Added "clean -purge" and ";;;" supportClifford Wolf2013-08-11
* Added ";;" as shortcut for "; clean;"Clifford Wolf2013-08-11
* freduce performance fixClifford Wolf2013-08-10
* Added techmap -opt modeClifford Wolf2013-08-09
* Some fixes to improve determinismClifford Wolf2013-08-09
* Sort ctrl signals in fsm_extractClifford Wolf2013-08-08
* Added -try option to freduce passClifford Wolf2013-08-08
* Added "clean" command (less verbose opt_clean)Clifford Wolf2013-08-08
* Fixed topological ordering in freduce passClifford Wolf2013-08-07
* Improved handling of private names in opt_clean and rename commandsClifford Wolf2013-08-07
* Small bugfixes in freduce passClifford Wolf2013-08-06
* Added freduce commandClifford Wolf2013-08-06
* Added "design" command (-reset, -save, -load)Clifford Wolf2013-07-27
* Automatically run "proc" on extract map filesClifford Wolf2013-07-24
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-23
* Bugfixes for empty signal vectorsClifford Wolf2013-07-10
* Added opt_clean -purge optionClifford Wolf2013-07-07
* Fixed handling of $eq and $ne in opt_constClifford Wolf2013-07-07
* Added SAT support for -all/-max with -verifyClifford Wolf2013-06-23
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-06-20
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| * Added renaming of wires and cells to "rename" commandClifford Wolf2013-06-19