index
:
yosys
master
Debian dgit repo for package yosys
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
passes
Commit message (
Expand
)
Author
Age
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Added techmap -extern
Clifford Wolf
2014-07-27
*
Added topological sorting to techmap
Clifford Wolf
2014-07-27
*
Added SigPool::check(bit)
Clifford Wolf
2014-07-27
*
Fixed bug in opt_clean
Clifford Wolf
2014-07-27
*
Improved performance of opt_const on large modules
Clifford Wolf
2014-07-27
*
Fixed a bug in opt_clean and some RTLIL API usage cleanups
Clifford Wolf
2014-07-27
*
Added log_cmd_error_expection
Clifford Wolf
2014-07-27
*
Using new obj iterator API in a few places
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed more code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
More RTLIL::Cell API usage cleanups
Clifford Wolf
2014-07-26
*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Added copy-constructor-like module->addCell(name, other) method
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Various RTLIL::SigSpec related code cleanups
Clifford Wolf
2014-07-25
*
Fixed memory corruption in "opt_reduce" pass
Clifford Wolf
2014-07-25
*
Disabled cover() for non-linux builds
Clifford Wolf
2014-07-25
*
Improvements in "cover" command
Clifford Wolf
2014-07-25
*
Replaced more old SigChunk programming patterns
Clifford Wolf
2014-07-24
*
Added cover() calls to opt_const
Clifford Wolf
2014-07-24
*
Added "make SMALL=1"
Clifford Wolf
2014-07-24
*
Added "make PRETTY=1"
Clifford Wolf
2014-07-24
*
Added "cover" command
Clifford Wolf
2014-07-24
*
Various small fixes (from gcc compiler warnings)
Clifford Wolf
2014-07-23
*
Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
*
Removed RTLIL::SigSpec::expand() method
Clifford Wolf
2014-07-23
*
Fixed all users of SigSpec::chunks_rw() and removed it
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
Clifford Wolf
2014-07-23
*
SigSpec refactoring: cleanup of old SigSpec usage in fsm_* commands
Clifford Wolf
2014-07-22
*
Fixed memory corruption with new SigSpec API in proc_mux
Clifford Wolf
2014-07-22
*
fixed memory leak in fsm_opt
Clifford Wolf
2014-07-22
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
Added "opt_const -keepdc"
Clifford Wolf
2014-07-21
*
Added mul to mux conversion to "opt_const -fine"
Clifford Wolf
2014-07-21
*
Added "opt_const -fine" and "opt_reduce -fine"
Clifford Wolf
2014-07-21
*
Added opt_const support for simple identities
Clifford Wolf
2014-07-21
*
Replaced depricated NEW_WIRE macro with module->addWire() calls
Clifford Wolf
2014-07-21
*
Removed deprecated module->new_wire()
Clifford Wolf
2014-07-21
*
Wider range of cell types supported in "share" pass
Clifford Wolf
2014-07-21
[next]