yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added "abc -fast"	Clifford Wolf	2014-09-18
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*	Fixed $_NOR vs. $_NOR_ typo in abc.cc	Clifford Wolf	2014-09-16
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*	Fixed $memwr/$memrd order in memory_dff	Clifford Wolf	2014-09-16
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*	More aggressive $macc merging in alumacc	Clifford Wolf	2014-09-15
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*	Added the obvious optimizations to alumacc $macc generator	Clifford Wolf	2014-09-15
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*	Improved maccmap tree bit packing	Clifford Wolf	2014-09-15
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*	Fixed wreduce $shiftx handling	Clifford Wolf	2014-09-15
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*	Fixed techmap_wrap for techmap_celltype	Clifford Wolf	2014-09-14
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*	Various fixes/cleanups in alumacc and maccmap	Clifford Wolf	2014-09-14
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*	Added techmap_wrap attribute	Clifford Wolf	2014-09-14
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*	alumacc fix for $pos cells	Clifford Wolf	2014-09-14
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*	Extract $alu cells in alumacc	Clifford Wolf	2014-09-14
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*	Merge $macc cells in alumacc pass	Clifford Wolf	2014-09-14
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*	Basic $macc extract in alumacc	Clifford Wolf	2014-09-14
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*	alumacc skeleton	Clifford Wolf	2014-09-14
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*	Cleanup in wreduce	Clifford Wolf	2014-09-14
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*	Added $lcu cell type	Clifford Wolf	2014-09-08
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*	Added "$fa" cell type	Clifford Wolf	2014-09-08
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*	Trim msb/lsb zero bits from full adder in maccmap	Clifford Wolf	2014-09-08
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*	Added "test_cell -const"	Clifford Wolf	2014-09-08
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*	Added 'techmap_maccmap' techmap attribute	Clifford Wolf	2014-09-07
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*	Added "maccmap" command	Clifford Wolf	2014-09-07
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*	Added "test_cell -nosat"	Clifford Wolf	2014-09-07
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*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06
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*	Added $macc SAT model	Clifford Wolf	2014-09-06
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*	Added $macc cell type	Clifford Wolf	2014-09-06
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-09-06
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\| *	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
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* \|	Added "test_cell -script"	Clifford Wolf	2014-09-06
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*	Fixed "opt_const -fine" for $pos cells	Clifford Wolf	2014-09-04
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
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*	Fixed "test_cells -vlog"	Clifford Wolf	2014-09-03
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*	Improvements in "test_cell -vlog"	Clifford Wolf	2014-09-02
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*	Added test_cell -vlog	Clifford Wolf	2014-09-02
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*	Added SAT testing to test_cell eval stage	Clifford Wolf	2014-09-02
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*	Removed references to yosys-svgviewer from docs	Clifford Wolf	2014-09-02
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*	Using "xdot" instead of "yosys-svgviewer" in show command	Clifford Wolf	2014-09-02
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*	Added $alu support to test_cell	Clifford Wolf	2014-09-01
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*	Added "test_cell -simlib -v"	Clifford Wolf	2014-09-01
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*	Added "techmap -autoproc"	Clifford Wolf	2014-09-01
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*	Fixes in old SAT example.ys	Clifford Wolf	2014-09-01
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*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01
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*	Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵	Clifford Wolf	2014-09-01
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*	Added eval testing to test_cell	Clifford Wolf	2014-08-31
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*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31
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*	Added design->scratchpad	Clifford Wolf	2014-08-30
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*	Improved write address decoder generation memory_map	Clifford Wolf	2014-08-30
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*	Using worker class in memory_map	Clifford Wolf	2014-08-30
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*	Don't change existing binary FSM encoding if it is already optimal	Clifford Wolf	2014-08-30
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*	Using $pmux info in fsm_extract to optimize transition ctrl_in patterns	Clifford Wolf	2014-08-30
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