yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added "show -signed"	Clifford Wolf	2014-08-04
*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04
*	Fixed "share" for memory read ports	Clifford Wolf	2014-08-03
*	Progress in "wreduce" pass	Clifford Wolf	2014-08-03
*	Added "wreduce" command (work in progress)	Clifford Wolf	2014-08-03
*	Implemented recursive techmap	Clifford Wolf	2014-08-03
*	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03
*	Implemented simplemap support for "techmap -extern"	Clifford Wolf	2014-08-02
*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02
*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
*	Fixed a performance bug in opt_reduce	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01
*	Added "test_autotb -n <num_iter>" option	Clifford Wolf	2014-08-01
*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Added "trace" command	Clifford Wolf	2014-07-31
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31
*	Added "techmap -assert"	Clifford Wolf	2014-07-31
*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30
*	Added write_file command	Clifford Wolf	2014-07-30
*	Improvements in test_cell	Clifford Wolf	2014-07-30
*	Added "test_cell" command	Clifford Wolf	2014-07-29
*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29
*	Allow "hierarchy -generate" for $__ cells	Clifford Wolf	2014-07-29
*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Added techmap -extern	Clifford Wolf	2014-07-27
*	Added topological sorting to techmap	Clifford Wolf	2014-07-27
*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27
*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27
*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27
*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27
*	Added log_cmd_error_expection	Clifford Wolf	2014-07-27
*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26