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* Added "test_cell -simlib -v"Clifford Wolf2014-09-01
* Added "techmap -autoproc"Clifford Wolf2014-09-01
* Fixes in old SAT example.ysClifford Wolf2014-09-01
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-01
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-01
* Added eval testing to test_cellClifford Wolf2014-08-31
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-31
* Added design->scratchpadClifford Wolf2014-08-30
* Improved write address decoder generation memory_mapClifford Wolf2014-08-30
* Using worker class in memory_mapClifford Wolf2014-08-30
* Don't change existing binary FSM encoding if it is already optimalClifford Wolf2014-08-30
* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-30
* Improved handling of $pmux cells in fsm_extractClifford Wolf2014-08-30
* Fixed inserting of Q-inverters in dfflibmapClifford Wolf2014-08-27
* Implemented "rename -enumerate -pattern"Clifford Wolf2014-08-26
* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-24
* Added some additional log messages to opt_constClifford Wolf2014-08-24
* azonenberg: Make dump_vcd save model when temporal induction fails due to ste...Clifford Wolf2014-08-24
* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-23
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
* Added "stat -width"Clifford Wolf2014-08-22
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-22
* Added "plugin" commandClifford Wolf2014-08-22
* Renamed toposort.h to utils.hClifford Wolf2014-08-17
* Added module->uniquify()Clifford Wolf2014-08-16
* Added "test_cell -s <seed>"Clifford Wolf2014-08-16
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16
* Added "opt -fast"Clifford Wolf2014-08-16
* Bugfix in iopadmapClifford Wolf2014-08-15
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
* document "techmap -map %<design-name>"Clifford Wolf2014-08-15
* Added module->portsClifford Wolf2014-08-14
* RIP $safe_pmuxClifford Wolf2014-08-14
* Some improvements in FSM mapping and recodingClifford Wolf2014-08-14
* Added "abc -D" for setting delay targetClifford Wolf2014-08-14
* Filter ANSI escape sequences from ABC outputClifford Wolf2014-08-13
* Fixed handling of constant-true branches in proc_cleanClifford Wolf2014-08-12
* Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-10
* Fixed "share" for complex scenarios with never-active cellsClifford Wolf2014-08-09
* Do not share any $reduce_* cells (its complicated and not worth it anyways)Clifford Wolf2014-08-09
* Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-09
* Another fsm_extract bugfixClifford Wolf2014-08-08
* Fixed "fsm -export"Clifford Wolf2014-08-08
* Fixed sharing of reduce operatorClifford Wolf2014-08-08
* Fixed fsm_extract for wreduced muxesClifford Wolf2014-08-08
* Added "sat -prove-skip"Clifford Wolf2014-08-08
* Fixed build with gcc-4.6Clifford Wolf2014-08-07