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* Added online help for "show" and "hierarchy" commandsClifford Wolf2013-02-28
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* Added help for command line optionsClifford Wolf2013-02-28
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* Added more help messages (extract, abc, dfflibmap)Clifford Wolf2013-02-28
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* Added port swapping and compatible types to "extract" passClifford Wolf2013-02-28
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* Added "extract -constports" featureClifford Wolf2013-02-27
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* Fixed "extract" pass for non-optimized needlesClifford Wolf2013-02-27
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* Added support for simple gates with one constant input to opt_constClifford Wolf2013-02-27
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* Added extract -verbose and -map ilang supportClifford Wolf2013-02-27
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* Implemented basic functionality of "extract" passClifford Wolf2013-02-27
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* Added support for constant signals in "extract" passClifford Wolf2013-02-27
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* Added "extract" pass (not functional yet)Clifford Wolf2013-02-27
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* Moved stand-alone libs to libs/ directory and added libs/subcircuitClifford Wolf2013-02-27
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* "fsm_export" pass: fix KISS file generation.Martin Schmölzer2013-02-23
| | | | | | | | | | | The KISS file format now follows the conventions specified in "Logic Synthesis and Optimization Benchmarks User Guide", Version 3.0 by Saeyang Yang. This change ensures interoperability with the "trfsmgen" program by Johann Glaser. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
* Add support for "fsm_export" synthesis attributes to fsm_export pass.Martin Schmölzer2013-01-08
| | | | | | | | | | | | | | This allows to specify the file name for exported files directly in the HDL source via the fsm_export=... attribute on the FSM state register. Verilog example: (* fsm_export="my_fsm.kiss2" *) reg [3:0] state; The fsm_export pass now also accepts the option "-noauto". This causes only FSMs with the fsm_export attribute to be exported, any other FSMs are ignored. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
* Copy attributes from state signal to fsm cellClifford Wolf2013-01-05
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* added .gitignore filesClifford Wolf2013-01-05
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* initial importClifford Wolf2013-01-05