yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Fixed detection of public wires in opt_rmunused	Clifford Wolf	2013-03-10
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*	Automatically select new objects in abc and techmap passes	Clifford Wolf	2013-03-08
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*	Split extract -attr into extract -cell_attr and -wire_attr	Clifford Wolf	2013-03-08
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*	Added support for attribute matching in extract pass	Clifford Wolf	2013-03-07
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*	Changed default value for extract -mine_cells_span	Clifford Wolf	2013-03-05
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*	Implemented -mine_split option to extract pass	Clifford Wolf	2013-03-05
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*	Implemented much better #x select operator	Clifford Wolf	2013-03-05
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*	Implemented extract -mine_max_fanout <num> option	Clifford Wolf	2013-03-03
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*	Added "shared nodes" feature to the subcircuit library	Clifford Wolf	2013-03-03
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*	Added support for "extract_order" attribute to extract pass	Clifford Wolf	2013-03-03
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*	Added design->select() api and use it in extract pass	Clifford Wolf	2013-03-03
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*	Minor hotfixes (mostly gcc build fixes)	Clifford Wolf	2013-03-03
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*	Added library support to celltypes class and show pass	Clifford Wolf	2013-03-03
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*	Implemented general handler for selection arguments	Clifford Wolf	2013-03-03
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*	Finished "extract -mine" feature	Clifford Wolf	2013-03-02
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*	Added -mine option to extract pass (not finished)	Clifford Wolf	2013-03-02
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*	Added help messages for fsm_* passes	Clifford Wolf	2013-03-01
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*	Added help messages to memory_* passes	Clifford Wolf	2013-03-01
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*	Added help messages to proc_* passes	Clifford Wolf	2013-03-01
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*	Added help messages for opt_* passes	Clifford Wolf	2013-03-01
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*	Added more help messages	Clifford Wolf	2013-03-01
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*	Added online help for "show" and "hierarchy" commands	Clifford Wolf	2013-02-28
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*	Added help for command line options	Clifford Wolf	2013-02-28
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*	Added more help messages (extract, abc, dfflibmap)	Clifford Wolf	2013-02-28
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*	Added port swapping and compatible types to "extract" pass	Clifford Wolf	2013-02-28
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*	Added "extract -constports" feature	Clifford Wolf	2013-02-27
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*	Fixed "extract" pass for non-optimized needles	Clifford Wolf	2013-02-27
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*	Added support for simple gates with one constant input to opt_const	Clifford Wolf	2013-02-27
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*	Added extract -verbose and -map ilang support	Clifford Wolf	2013-02-27
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*	Implemented basic functionality of "extract" pass	Clifford Wolf	2013-02-27
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*	Added support for constant signals in "extract" pass	Clifford Wolf	2013-02-27
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*	Added "extract" pass (not functional yet)	Clifford Wolf	2013-02-27
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*	Moved stand-alone libs to libs/ directory and added libs/subcircuit	Clifford Wolf	2013-02-27
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*	"fsm_export" pass: fix KISS file generation.	Martin Schmölzer	2013-02-23
\| \| \| \| \| \| \| \| \| \| \|	The KISS file format now follows the conventions specified in "Logic Synthesis and Optimization Benchmarks User Guide", Version 3.0 by Saeyang Yang. This change ensures interoperability with the "trfsmgen" program by Johann Glaser. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
*	Add support for "fsm_export" synthesis attributes to fsm_export pass.	Martin Schmölzer	2013-01-08
\| \| \| \| \| \| \| \| \| \| \| \| \| \|	This allows to specify the file name for exported files directly in the HDL source via the fsm_export=... attribute on the FSM state register. Verilog example: (* fsm_export="my_fsm.kiss2" *) reg [3:0] state; The fsm_export pass now also accepts the option "-noauto". This causes only FSMs with the fsm_export attribute to be exported, any other FSMs are ignored. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
*	Copy attributes from state signal to fsm cell	Clifford Wolf	2013-01-05
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*	added .gitignore files	Clifford Wolf	2013-01-05
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*	initial import	Clifford Wolf	2013-01-05