yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	improved opt_reduce for $mem/$memwr WR_EN multiplexers	Clifford Wolf	2014-07-16
*	Changes to "memory" pass for new $memwr/$mem WR_EN interface	Clifford Wolf	2014-07-16
*	now ignore init attributes on non-register wires in sat command	Clifford Wolf	2014-07-05
*	Do not create $dffsr cells with no-op resets in proc_dff	Clifford Wolf	2014-06-19
*	Added %D and %c select commands	Clifford Wolf	2014-06-14
*	fixed cell array handling of positional arguments	Clifford Wolf	2014-06-07
*	Add support for cell arrays	Clifford Wolf	2014-06-07
*	added tee cmd	Clifford Wolf	2014-06-03
*	Fixed log messages in memory_dff	Clifford Wolf	2014-06-01
*	added log_header to miter and expose pass, show cell type for exposed ports	Johann Glaser	2014-05-28
*	be more verbose when techmap yielded processes	Johann Glaser	2014-05-26
*	Fixed bug in opt_reduce (see vloghammer issue_044)	Clifford Wolf	2014-05-12
*	fixed syntax error in dot file created by "show" command	Clifford Wolf	2014-05-10
*	Fixed performance problem in opt_mux with nets driven by many conflicting dri...	Clifford Wolf	2014-03-19
*	Small improvement in SAT log messages	Clifford Wolf	2014-03-13
*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13
*	- kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...	Siesh1oo	2014-03-12
*	OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/...	Clifford Wolf	2014-03-11
*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11
*	Fixed memory corruption in passes/abc/blifparse.cc	Clifford Wolf	2014-03-11
*	Fixed dumping of timing() { .. } block in libparse	Clifford Wolf	2014-03-09
*	Verbose reading of liberty and constr files in ABC pass	Clifford Wolf	2014-03-09
*	Fixed bug in freduce command	Clifford Wolf	2014-03-07
*	Some minor code cleanups in freduce command	Clifford Wolf	2014-03-07
*	Added freduce -dump	Clifford Wolf	2014-03-06
*	Added freduce -stop	Clifford Wolf	2014-03-06
*	Fixed undef handling in opt_reduce	Clifford Wolf	2014-03-06
*	Added techmap -max_iter option	Clifford Wolf	2014-03-06
*	fixed freduce for Minisat::SimpSolver: use frozen_literal()	Clifford Wolf	2014-03-03
*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27
*	Fixed bug (typo) in passes/opt/opt_const.cc	Clifford Wolf	2014-02-22
*	Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst	Clifford Wolf	2014-02-21
*	Added _TECHMAP_REPLACE_ feature to techmap	Clifford Wolf	2014-02-20
*	Added "extract -ignore_parameters" and "extract -ignore_param ..."	Clifford Wolf	2014-02-20
*	Added "extract -map %<design_name>"	Clifford Wolf	2014-02-20
*	Added "design -push" and "design -pop"	Clifford Wolf	2014-02-20
*	Added connwrappers command	Clifford Wolf	2014-02-20
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-02-18
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\| *	Added "sat -dump_cnf"	Clifford Wolf	2014-02-18
\| *	Coding style corrections in SatHelper::dump_model_to_vcd()	Clifford Wolf	2014-02-18
\| *	Added "sat -initsteps"	Clifford Wolf	2014-02-18
* \|	Added techmap support for _TECHMAP_CONNMAP_*_	Clifford Wolf	2014-02-18
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*	Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups	Clifford Wolf	2014-02-17
*	Added "-dump_fail_to_vcd" argument to SAT solver	Andrew Zonenberg	2014-02-17
*	Better preserve wires when flattening (in comparison to techmap)	Clifford Wolf	2014-02-17
*	Added some additional checks to techmap	Clifford Wolf	2014-02-16
*	Added CONSTMSK and CONSTVAL feature to techmap	Clifford Wolf	2014-02-16
*	Fixed handling of "keep" attribute on wires in opt_clean	Clifford Wolf	2014-02-16
*	Fixed use of selection in splitnets command	Clifford Wolf	2014-02-16
*	Added recursion support to techmap	Clifford Wolf	2014-02-16