yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
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*	Do not introduce new logic loops in "share"	Clifford Wolf	2014-09-21
*	Assert on new logic loops in "share" pass	Clifford Wolf	2014-09-21
*	Added "test_abcloop" command	Clifford Wolf	2014-09-19
*	Small improvements in "abc" command handle_loops() function	Clifford Wolf	2014-09-19
*	Using "NOT" instead of "INV" as cell name in default abc genlib file	Clifford Wolf	2014-09-19
*	Alphabetically sort port names in "show" output	Clifford Wolf	2014-09-19
*	Do not run "scorr" in "abc -fast"	Clifford Wolf	2014-09-18
*	Added "abc -fast"	Clifford Wolf	2014-09-18
*	Fixed $_NOR vs. $_NOR_ typo in abc.cc	Clifford Wolf	2014-09-16
*	Fixed $memwr/$memrd order in memory_dff	Clifford Wolf	2014-09-16
*	More aggressive $macc merging in alumacc	Clifford Wolf	2014-09-15
*	Added the obvious optimizations to alumacc $macc generator	Clifford Wolf	2014-09-15
*	Improved maccmap tree bit packing	Clifford Wolf	2014-09-15
*	Fixed wreduce $shiftx handling	Clifford Wolf	2014-09-15
*	Fixed techmap_wrap for techmap_celltype	Clifford Wolf	2014-09-14
*	Various fixes/cleanups in alumacc and maccmap	Clifford Wolf	2014-09-14
*	Added techmap_wrap attribute	Clifford Wolf	2014-09-14
*	alumacc fix for $pos cells	Clifford Wolf	2014-09-14
*	Extract $alu cells in alumacc	Clifford Wolf	2014-09-14
*	Merge $macc cells in alumacc pass	Clifford Wolf	2014-09-14
*	Basic $macc extract in alumacc	Clifford Wolf	2014-09-14
*	alumacc skeleton	Clifford Wolf	2014-09-14
*	Cleanup in wreduce	Clifford Wolf	2014-09-14
*	Added $lcu cell type	Clifford Wolf	2014-09-08
*	Added "$fa" cell type	Clifford Wolf	2014-09-08
*	Trim msb/lsb zero bits from full adder in maccmap	Clifford Wolf	2014-09-08
*	Added "test_cell -const"	Clifford Wolf	2014-09-08
*	Added 'techmap_maccmap' techmap attribute	Clifford Wolf	2014-09-07
*	Added "maccmap" command	Clifford Wolf	2014-09-07
*	Added "test_cell -nosat"	Clifford Wolf	2014-09-07
*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06
*	Added $macc SAT model	Clifford Wolf	2014-09-06
*	Added $macc cell type	Clifford Wolf	2014-09-06
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-09-06
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\| *	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
* \|	Added "test_cell -script"	Clifford Wolf	2014-09-06
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*	Fixed "opt_const -fine" for $pos cells	Clifford Wolf	2014-09-04
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
*	Fixed "test_cells -vlog"	Clifford Wolf	2014-09-03
*	Improvements in "test_cell -vlog"	Clifford Wolf	2014-09-02
*	Added test_cell -vlog	Clifford Wolf	2014-09-02
*	Added SAT testing to test_cell eval stage	Clifford Wolf	2014-09-02
*	Removed references to yosys-svgviewer from docs	Clifford Wolf	2014-09-02
*	Using "xdot" instead of "yosys-svgviewer" in show command	Clifford Wolf	2014-09-02
*	Added $alu support to test_cell	Clifford Wolf	2014-09-01
*	Added "test_cell -simlib -v"	Clifford Wolf	2014-09-01
*	Added "techmap -autoproc"	Clifford Wolf	2014-09-01
*	Fixes in old SAT example.ys	Clifford Wolf	2014-09-01
*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01