yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15
*	document "techmap -map %<design-name>"	Clifford Wolf	2014-08-15
*	Added module->ports	Clifford Wolf	2014-08-14
*	RIP $safe_pmux	Clifford Wolf	2014-08-14
*	Some improvements in FSM mapping and recoding	Clifford Wolf	2014-08-14
*	Added "abc -D" for setting delay target	Clifford Wolf	2014-08-14
*	Filter ANSI escape sequences from ABC output	Clifford Wolf	2014-08-13
*	Fixed handling of constant-true branches in proc_clean	Clifford Wolf	2014-08-12
*	Fixed FSM mapping for multiple reset-like signals	Clifford Wolf	2014-08-10
*	Fixed "share" for complex scenarios with never-active cells	Clifford Wolf	2014-08-09
*	Do not share any $reduce_* cells (its complicated and not worth it anyways)	Clifford Wolf	2014-08-09
*	Some improvements in fsm_opt and fsm_map for FSM with unreachable states	Clifford Wolf	2014-08-09
*	Another fsm_extract bugfix	Clifford Wolf	2014-08-08
*	Fixed "fsm -export"	Clifford Wolf	2014-08-08
*	Fixed sharing of reduce operator	Clifford Wolf	2014-08-08
*	Fixed fsm_extract for wreduced muxes	Clifford Wolf	2014-08-08
*	Added "sat -prove-skip"	Clifford Wolf	2014-08-08
*	Fixed build with gcc-4.6	Clifford Wolf	2014-08-07
*	Use "-keepdc" in "miter -equiv -flatten"	Clifford Wolf	2014-08-07
*	Various improvements in memory_dff pass	Clifford Wolf	2014-08-06
*	Various fixes and improvements in wreduce pass	Clifford Wolf	2014-08-05
*	Removed old "constmap" from wreduce code	Clifford Wolf	2014-08-05
*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05
*	Cleanups and improvements in wreduce pass	Clifford Wolf	2014-08-05
*	Added mux support to wreduce command	Clifford Wolf	2014-08-05
*	Added "show -signed"	Clifford Wolf	2014-08-04
*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04
*	Fixed "share" for memory read ports	Clifford Wolf	2014-08-03
*	Progress in "wreduce" pass	Clifford Wolf	2014-08-03
*	Added "wreduce" command (work in progress)	Clifford Wolf	2014-08-03
*	Implemented recursive techmap	Clifford Wolf	2014-08-03
*	Fixes in show command (related to new IdString)	Clifford Wolf	2014-08-03
*	Implemented simplemap support for "techmap -extern"	Clifford Wolf	2014-08-02
*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02
*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
*	Fixed a performance bug in opt_reduce	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02
*	Replaced sha1 implementation	Clifford Wolf	2014-08-01
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01
*	Added "test_autotb -n <num_iter>" option	Clifford Wolf	2014-08-01
*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Added "trace" command	Clifford Wolf	2014-07-31
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31
*	Added "techmap -assert"	Clifford Wolf	2014-07-31