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* Added "sat -prove-skip"Clifford Wolf2014-08-08
* Fixed build with gcc-4.6Clifford Wolf2014-08-07
* Use "-keepdc" in "miter -equiv -flatten"Clifford Wolf2014-08-07
* Various improvements in memory_dff passClifford Wolf2014-08-06
* Various fixes and improvements in wreduce passClifford Wolf2014-08-05
* Removed old "constmap" from wreduce codeClifford Wolf2014-08-05
* Added support for truncating of wires to wreduce passClifford Wolf2014-08-05
* Cleanups and improvements in wreduce passClifford Wolf2014-08-05
* Added mux support to wreduce commandClifford Wolf2014-08-05
* Added "show -signed"Clifford Wolf2014-08-04
* Added RTLIL::IdString::in(...)Clifford Wolf2014-08-04
* Fixed "share" for memory read portsClifford Wolf2014-08-03
* Progress in "wreduce" passClifford Wolf2014-08-03
* Added "wreduce" command (work in progress)Clifford Wolf2014-08-03
* Implemented recursive techmapClifford Wolf2014-08-03
* Fixes in show command (related to new IdString)Clifford Wolf2014-08-03
* Implemented simplemap support for "techmap -extern"Clifford Wolf2014-08-02
* Bugfix in "techmap -extern"Clifford Wolf2014-08-02
* Removed at() method from RTLIL::IdStringClifford Wolf2014-08-02
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
* Fixed a performance bug in opt_reduceClifford Wolf2014-08-02
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-02
* Replaced sha1 implementationClifford Wolf2014-08-01
* Added ModIndex helper class, some changes to RTLIL::MonitorClifford Wolf2014-08-01
* Added "test_autotb -n <num_iter>" optionClifford Wolf2014-08-01
* Renamed modwalker.h to modtools.hClifford Wolf2014-07-31
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added "trace" commandClifford Wolf2014-07-31
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
* Added "techmap -assert"Clifford Wolf2014-07-31
* Added techmap CONSTMAP featureClifford Wolf2014-07-30
* Added write_file commandClifford Wolf2014-07-30
* Improvements in test_cellClifford Wolf2014-07-30
* Added "test_cell" commandClifford Wolf2014-07-29
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-29
* Allow "hierarchy -generate" for $__ cellsClifford Wolf2014-07-29
* Added "techmap -map %{design-name}"Clifford Wolf2014-07-29
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Added techmap -externClifford Wolf2014-07-27
* Added topological sorting to techmapClifford Wolf2014-07-27
* Added SigPool::check(bit)Clifford Wolf2014-07-27
* Fixed bug in opt_cleanClifford Wolf2014-07-27
* Improved performance of opt_const on large modulesClifford Wolf2014-07-27
* Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-27
* Added log_cmd_error_expectionClifford Wolf2014-07-27