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* Implemented read_verilog -deferClifford Wolf2014-02-13
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* Removed double blanks in ABC default command sequencesClifford Wolf2014-02-13
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* Updated ABC and some related changesClifford Wolf2014-02-13
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* Updated ABC to rev e97a6e1d59b9Clifford Wolf2014-02-12
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* Various improvements in expose command (added -sep and -cut)Clifford Wolf2014-02-09
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* Added delete {-input|-output|-port}Clifford Wolf2014-02-09
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* Bugfix in delete commandClifford Wolf2014-02-09
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* Fixed handling of async reset in expose -evert-dffClifford Wolf2014-02-08
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* Build fixes for log cmdClifford Wolf2014-02-08
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-08
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| * added "log" commandJohann Glaser2014-02-08
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* | Implemented expose -evert-dffClifford Wolf2014-02-08
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* | Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collectClifford Wolf2014-02-08
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* Added various new options to splice commandClifford Wolf2014-02-08
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* Added %a select operatorClifford Wolf2014-02-08
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* Moved some passes to other source directoriesClifford Wolf2014-02-08
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* Added support for "keep" attribute to abc passClifford Wolf2014-02-08
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* Added opt -purge (frontend to opt_clean -purge)Clifford Wolf2014-02-08
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* Only count non-trivial attributes when findinf master signal in opt_cleanClifford Wolf2014-02-08
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* Now also move net labes to the right position in splice cmdClifford Wolf2014-02-08
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* Improved detection of primary wire for a signal in opt_cleanClifford Wolf2014-02-07
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* Added splice commandClifford Wolf2014-02-07
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* Added log_header() to splitnetsClifford Wolf2014-02-07
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* Added $slice and $concat cell typesClifford Wolf2014-02-07
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* Re-enabled abc "retime" after sorting yout the yosys-bigsim problemClifford Wolf2014-02-07
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* Fixed use of "cmd_error" in passes/cmds/design.ccClifford Wolf2014-02-07
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* Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim ↵Clifford Wolf2014-02-06
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* Added "retime" to standard ABC recipesClifford Wolf2014-02-06
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* Added copy commandClifford Wolf2014-02-06
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* Added design -stash/-copy-from/-copy-toClifford Wolf2014-02-06
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* Added support for s: select expressions (wire width)Clifford Wolf2014-02-06
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* Added i:, o:, and x: selection patternClifford Wolf2014-02-06
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* Added support for %m selection opClifford Wolf2014-02-06
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-06
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| * new %s: add sub-modules to selectionJohann Glaser2014-02-06
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* | Added generic RTLIL::SigSpec::parse_sel() with support for selection variablesClifford Wolf2014-02-06
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* Added support for sat -show @<sel_name>Clifford Wolf2014-02-06
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* Added sat -set-init-def and sat -tempinduct-defClifford Wolf2014-02-06
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* Added opt_const -undrivenClifford Wolf2014-02-06
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* Added expose -dffClifford Wolf2014-02-06
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* Changed techmap description from "simple" to "generic"Clifford Wolf2014-02-06
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* Added miter -make_outcmpClifford Wolf2014-02-06
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* Added sat -set-init-zero supportClifford Wolf2014-02-06
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* Added sat -verify and -falsify support for non-prove casesClifford Wolf2014-02-06
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* Added expose commandClifford Wolf2014-02-05
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* Simplified select "Assertation failed" message generationClifford Wolf2014-02-05
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-05
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| * be more verbose for select -assert-any and -assert-noneJohann Glaser2014-02-05
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| * improved help for "select"Johann Glaser2014-02-05
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* | Added selection support for r: and selection with relational operatorsClifford Wolf2014-02-05
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