path: root/passes
Commit message (Expand)AuthorAge
* Added 'techmap_maccmap' techmap attributeClifford Wolf2014-09-07
* Added "maccmap" commandClifford Wolf2014-09-07
* Added "test_cell -nosat"Clifford Wolf2014-09-07
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-06
* Added $macc SAT modelClifford Wolf2014-09-06
* Added $macc cell typeClifford Wolf2014-09-06
* Merge branch 'master' of Wolf2014-09-06
| * Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
* | Added "test_cell -script"Clifford Wolf2014-09-06
* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-04
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Fixed "test_cells -vlog"Clifford Wolf2014-09-03
* Improvements in "test_cell -vlog"Clifford Wolf2014-09-02
* Added test_cell -vlogClifford Wolf2014-09-02
* Added SAT testing to test_cell eval stageClifford Wolf2014-09-02
* Removed references to yosys-svgviewer from docsClifford Wolf2014-09-02
* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-02
* Added $alu support to test_cellClifford Wolf2014-09-01
* Added "test_cell -simlib -v"Clifford Wolf2014-09-01
* Added "techmap -autoproc"Clifford Wolf2014-09-01
* Fixes in old SAT example.ysClifford Wolf2014-09-01
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-01
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-01
* Added eval testing to test_cellClifford Wolf2014-08-31
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-31
* Added design->scratchpadClifford Wolf2014-08-30
* Improved write address decoder generation memory_mapClifford Wolf2014-08-30
* Using worker class in memory_mapClifford Wolf2014-08-30
* Don't change existing binary FSM encoding if it is already optimalClifford Wolf2014-08-30
* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-30
* Improved handling of $pmux cells in fsm_extractClifford Wolf2014-08-30
* Fixed inserting of Q-inverters in dfflibmapClifford Wolf2014-08-27
* Implemented "rename -enumerate -pattern"Clifford Wolf2014-08-26
* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-24
* Added some additional log messages to opt_constClifford Wolf2014-08-24
* azonenberg: Make dump_vcd save model when temporal induction fails due to ste...Clifford Wolf2014-08-24
* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-23
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
* Added "stat -width"Clifford Wolf2014-08-22
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-22
* Added "plugin" commandClifford Wolf2014-08-22
* Renamed toposort.h to utils.hClifford Wolf2014-08-17
* Added module->uniquify()Clifford Wolf2014-08-16
* Added "test_cell -s <seed>"Clifford Wolf2014-08-16
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16
* Added "opt -fast"Clifford Wolf2014-08-16
* Bugfix in iopadmapClifford Wolf2014-08-15
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15