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* Added translation from read-feedback to en-signals in memory_shareClifford Wolf2014-07-18
* Improved seeding of color rng in show commandClifford Wolf2014-07-18
* Only create collision detect logic in memory_share if necessaryClifford Wolf2014-07-18
* Added memory_shareClifford Wolf2014-07-18
* Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN portClifford Wolf2014-07-18
* Improved opt_reduce handling of mem wr_en mux bitsClifford Wolf2014-07-17
* Added support for "blackbox" attribute to iopadmapClifford Wolf2014-07-17
* Added support for "blackbox" attribute to flatten/techmapClifford Wolf2014-07-17
* improved opt_reduce for $mem/$memwr WR_EN multiplexersClifford Wolf2014-07-16
* Changes to "memory" pass for new $memwr/$mem WR_EN interfaceClifford Wolf2014-07-16
* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-05
* Do not create $dffsr cells with no-op resets in proc_dffClifford Wolf2014-06-19
* Added %D and %c select commandsClifford Wolf2014-06-14
* fixed cell array handling of positional argumentsClifford Wolf2014-06-07
* Add support for cell arraysClifford Wolf2014-06-07
* added tee cmdClifford Wolf2014-06-03
* Fixed log messages in memory_dffClifford Wolf2014-06-01
* added log_header to miter and expose pass, show cell type for exposed portsJohann Glaser2014-05-28
* be more verbose when techmap yielded processesJohann Glaser2014-05-26
* Fixed bug in opt_reduce (see vloghammer issue_044)Clifford Wolf2014-05-12
* fixed syntax error in dot file created by "show" commandClifford Wolf2014-05-10
* Fixed performance problem in opt_mux with nets driven by many conflicting dri...Clifford Wolf2014-03-19
* Small improvement in SAT log messagesClifford Wolf2014-03-13
* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
* - kernel/register.h, kernel/driver.cc: refactor rewrite_yosys_exe()/get_shar...Siesh1oo2014-03-12
* OSX compatible creation of stdcells.inc, using code from github.com/Siesh1oo/...Clifford Wolf2014-03-11
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
* Fixed memory corruption in passes/abc/blifparse.ccClifford Wolf2014-03-11
* Fixed dumping of timing() { .. } block in libparseClifford Wolf2014-03-09
* Verbose reading of liberty and constr files in ABC passClifford Wolf2014-03-09
* Fixed bug in freduce commandClifford Wolf2014-03-07
* Some minor code cleanups in freduce commandClifford Wolf2014-03-07
* Added freduce -dumpClifford Wolf2014-03-06
* Added freduce -stopClifford Wolf2014-03-06
* Fixed undef handling in opt_reduceClifford Wolf2014-03-06
* Added techmap -max_iter optionClifford Wolf2014-03-06
* fixed freduce for Minisat::SimpSolver: use frozen_literal()Clifford Wolf2014-03-03
* Fixed const folding of $bu0 cellsClifford Wolf2014-02-27
* Fixed bug (typo) in passes/opt/opt_const.ccClifford Wolf2014-02-22
* Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arstClifford Wolf2014-02-21
* Added _TECHMAP_REPLACE_ feature to techmapClifford Wolf2014-02-20
* Added "extract -ignore_parameters" and "extract -ignore_param ..."Clifford Wolf2014-02-20
* Added "extract -map %<design_name>"Clifford Wolf2014-02-20
* Added "design -push" and "design -pop"Clifford Wolf2014-02-20
* Added connwrappers commandClifford Wolf2014-02-20
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-02-18
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| * Added "sat -dump_cnf"Clifford Wolf2014-02-18
| * Coding style corrections in SatHelper::dump_model_to_vcd()Clifford Wolf2014-02-18
| * Added "sat -initsteps"Clifford Wolf2014-02-18
* | Added techmap support for _TECHMAP_CONNMAP_*_Clifford Wolf2014-02-18
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