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Author
Age
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Using "xdot" instead of "yosys-svgviewer" in show command
Clifford Wolf
2014-09-02
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Added $alu support to test_cell
Clifford Wolf
2014-09-01
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Added "test_cell -simlib -v"
Clifford Wolf
2014-09-01
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Added "techmap -autoproc"
Clifford Wolf
2014-09-01
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Fixes in old SAT example.ys
Clifford Wolf
2014-09-01
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Moved "share" and "wreduce" to passes/opt/
Clifford Wolf
2014-09-01
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Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵
Clifford Wolf
2014-09-01
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RTLIL::SigChunk::data
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Added eval testing to test_cell
Clifford Wolf
2014-08-31
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Added $lut support in test_cell, techmap, satgen
Clifford Wolf
2014-08-31
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Added design->scratchpad
Clifford Wolf
2014-08-30
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Improved write address decoder generation memory_map
Clifford Wolf
2014-08-30
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Using worker class in memory_map
Clifford Wolf
2014-08-30
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Don't change existing binary FSM encoding if it is already optimal
Clifford Wolf
2014-08-30
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Using $pmux info in fsm_extract to optimize transition ctrl_in patterns
Clifford Wolf
2014-08-30
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Improved handling of $pmux cells in fsm_extract
Clifford Wolf
2014-08-30
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Fixed inserting of Q-inverters in dfflibmap
Clifford Wolf
2014-08-27
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Implemented "rename -enumerate -pattern"
Clifford Wolf
2014-08-26
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Optimize shift ops with constant rhs in opt_const
Clifford Wolf
2014-08-24
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Added some additional log messages to opt_const
Clifford Wolf
2014-08-24
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azonenberg: Make dump_vcd save model when temporal induction fails due to ↵
Clifford Wolf
2014-08-24
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step limit
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Only call proc_share_dirname() in techmap when necessary
Clifford Wolf
2014-08-23
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Changed frontend-api from FILE to std::istream
Clifford Wolf
2014-08-23
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Changed backend-api from FILE to std::ostream
Clifford Wolf
2014-08-23
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Added "stat -width"
Clifford Wolf
2014-08-22
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Added emscripten (emcc) support to build system and some build fixes
Clifford Wolf
2014-08-22
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Added "plugin" command
Clifford Wolf
2014-08-22
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Renamed toposort.h to utils.h
Clifford Wolf
2014-08-17
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Added module->uniquify()
Clifford Wolf
2014-08-16
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Added "test_cell -s <seed>"
Clifford Wolf
2014-08-16
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Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵
Clifford Wolf
2014-08-16
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$_OAI4_
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Added "opt -fast"
Clifford Wolf
2014-08-16
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Bugfix in iopadmap
Clifford Wolf
2014-08-15
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Renamed $lut ports to follow A-Y naming scheme
Clifford Wolf
2014-08-15
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Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
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More idstring sort_by_* helpers and fixed tpl ordering in techmap
Clifford Wolf
2014-08-15
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document "techmap -map %<design-name>"
Clifford Wolf
2014-08-15
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Added module->ports
Clifford Wolf
2014-08-14
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RIP $safe_pmux
Clifford Wolf
2014-08-14
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Some improvements in FSM mapping and recoding
Clifford Wolf
2014-08-14
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Added "abc -D" for setting delay target
Clifford Wolf
2014-08-14
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Filter ANSI escape sequences from ABC output
Clifford Wolf
2014-08-13
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Fixed handling of constant-true branches in proc_clean
Clifford Wolf
2014-08-12
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Fixed FSM mapping for multiple reset-like signals
Clifford Wolf
2014-08-10
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Fixed "share" for complex scenarios with never-active cells
Clifford Wolf
2014-08-09
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Do not share any $reduce_* cells (its complicated and not worth it anyways)
Clifford Wolf
2014-08-09
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Some improvements in fsm_opt and fsm_map for FSM with unreachable states
Clifford Wolf
2014-08-09
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Another fsm_extract bugfix
Clifford Wolf
2014-08-08
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Fixed "fsm -export"
Clifford Wolf
2014-08-08
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Fixed sharing of reduce operator
Clifford Wolf
2014-08-08
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Fixed fsm_extract for wreduced muxes
Clifford Wolf
2014-08-08
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