yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Improved maccmap tree bit packing	Clifford Wolf	2014-09-15
*	Fixed wreduce $shiftx handling	Clifford Wolf	2014-09-15
*	Fixed techmap_wrap for techmap_celltype	Clifford Wolf	2014-09-14
*	Various fixes/cleanups in alumacc and maccmap	Clifford Wolf	2014-09-14
*	Added techmap_wrap attribute	Clifford Wolf	2014-09-14
*	alumacc fix for $pos cells	Clifford Wolf	2014-09-14
*	Extract $alu cells in alumacc	Clifford Wolf	2014-09-14
*	Merge $macc cells in alumacc pass	Clifford Wolf	2014-09-14
*	Basic $macc extract in alumacc	Clifford Wolf	2014-09-14
*	alumacc skeleton	Clifford Wolf	2014-09-14
*	Cleanup in wreduce	Clifford Wolf	2014-09-14
*	Added $lcu cell type	Clifford Wolf	2014-09-08
*	Added "$fa" cell type	Clifford Wolf	2014-09-08
*	Trim msb/lsb zero bits from full adder in maccmap	Clifford Wolf	2014-09-08
*	Added "test_cell -const"	Clifford Wolf	2014-09-08
*	Added 'techmap_maccmap' techmap attribute	Clifford Wolf	2014-09-07
*	Added "maccmap" command	Clifford Wolf	2014-09-07
*	Added "test_cell -nosat"	Clifford Wolf	2014-09-07
*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06
*	Added $macc SAT model	Clifford Wolf	2014-09-06
*	Added $macc cell type	Clifford Wolf	2014-09-06
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2014-09-06
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\| *	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
* \|	Added "test_cell -script"	Clifford Wolf	2014-09-06
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*	Fixed "opt_const -fine" for $pos cells	Clifford Wolf	2014-09-04
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
*	Fixed "test_cells -vlog"	Clifford Wolf	2014-09-03
*	Improvements in "test_cell -vlog"	Clifford Wolf	2014-09-02
*	Added test_cell -vlog	Clifford Wolf	2014-09-02
*	Added SAT testing to test_cell eval stage	Clifford Wolf	2014-09-02
*	Removed references to yosys-svgviewer from docs	Clifford Wolf	2014-09-02
*	Using "xdot" instead of "yosys-svgviewer" in show command	Clifford Wolf	2014-09-02
*	Added $alu support to test_cell	Clifford Wolf	2014-09-01
*	Added "test_cell -simlib -v"	Clifford Wolf	2014-09-01
*	Added "techmap -autoproc"	Clifford Wolf	2014-09-01
*	Fixes in old SAT example.ys	Clifford Wolf	2014-09-01
*	Moved "share" and "wreduce" to passes/opt/	Clifford Wolf	2014-09-01
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01
*	Added eval testing to test_cell	Clifford Wolf	2014-08-31
*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31
*	Added design->scratchpad	Clifford Wolf	2014-08-30
*	Improved write address decoder generation memory_map	Clifford Wolf	2014-08-30
*	Using worker class in memory_map	Clifford Wolf	2014-08-30
*	Don't change existing binary FSM encoding if it is already optimal	Clifford Wolf	2014-08-30
*	Using $pmux info in fsm_extract to optimize transition ctrl_in patterns	Clifford Wolf	2014-08-30
*	Improved handling of $pmux cells in fsm_extract	Clifford Wolf	2014-08-30
*	Fixed inserting of Q-inverters in dfflibmap	Clifford Wolf	2014-08-27
*	Implemented "rename -enumerate -pattern"	Clifford Wolf	2014-08-26
*	Optimize shift ops with constant rhs in opt_const	Clifford Wolf	2014-08-24
*	Added some additional log messages to opt_const	Clifford Wolf	2014-08-24