summaryrefslogtreecommitdiff
path: root/techlibs/common
Commit message (Expand)AuthorAge
* New upstream version 0.9Ruben Undheim2019-10-18
* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Imported yosys 0.7Ruben Undheim2016-11-03
* Squashed commit of the following:Ruben Undheim2016-09-23
* Progress in cell library documentationClifford Wolf2016-02-01
* Run opt_const before check in default scriptsClifford Wolf2015-12-22
* Progress on cell help messagesClifford Wolf2015-10-20
* Progress on cell help messagesClifford Wolf2015-10-17
* Added "prep" commandClifford Wolf2015-10-14
* Added more cell descriptionsClifford Wolf2015-10-14
* Added first help messages for cell typesClifford Wolf2015-10-14
* Added read-enable to memory modelClifford Wolf2015-09-25
* Added $tribuf and $_TBUF_ sim modelsClifford Wolf2015-08-16
* Added $tribuf and $_TBUF_ cell typesClifford Wolf2015-08-16
* Another block of spelling fixesLarry Doolittle2015-08-14
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-12
* Added WORDS parameter to $meminitClifford Wolf2015-07-31
* Added "synth -nofsm"Clifford Wolf2015-07-02
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added "synth -nordff -noalumacc"Clifford Wolf2015-06-15
* Added simplemap $lut supportClifford Wolf2015-04-27
* make all vector-size related integer params in $mem sim model signedClifford Wolf2015-04-05
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-05
* Added $assume cell typeClifford Wolf2015-02-26
* Added "stat" to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
* Added final checks to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
* Smaller default parameters in $mem simlib modelClifford Wolf2015-02-15
* Added $meminit support to "memory" commandClifford Wolf2015-02-14
* Added $meminit cell typeClifford Wolf2015-02-14
* Added "check" commandClifford Wolf2015-02-13
* Some test related fixesClifford Wolf2015-02-12
* Added "make mklibyosys", some minor API changesClifford Wolf2015-02-01
* Added "fsm -encfile"Clifford Wolf2015-01-30
* Added $equiv cell typeClifford Wolf2015-01-19
* Added cells.libClifford Wolf2015-01-16
* Added add_share_file Makefile macroClifford Wolf2015-01-08
* Progress in memory_bramClifford Wolf2015-01-03
* Added proper clkpol support to memory_bramClifford Wolf2015-01-02
* New $mem simlib modelClifford Wolf2015-01-02
* Fixed simlib entries for $memrd and $memwrClifford Wolf2014-12-30
* Fixed build with SMALL=1Clifford Wolf2014-12-30
* Improvements in simplemap api, added $ne $nex $eq $eqx supportClifford Wolf2014-12-24
* Removed UTF-8 chars from techmap.vClifford Wolf2014-12-12
* Added $dffe cell typeClifford Wolf2014-12-08
* Added $_DFFE_??_ cell typesClifford Wolf2014-12-08
* Added "abc" label in synth scriptClifford Wolf2014-10-31
* Added "opt -full" alias for all more aggressive optimizationsClifford Wolf2014-10-31
* Added $_BUF_ cell typeClifford Wolf2014-10-03
* namespace YosysClifford Wolf2014-09-27